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IDT71V416L10Y8

P1-P3P4-P6P7-P9
AUGUST 2000
DSC-3624/04
1
©2000 Integrated Device Technology, Inc.
Features
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256K x 16 advanced high-speed CMOS Static RAM
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JEDEC Center Power / GND pinout for reduced noise.
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Equal access and cycle times
– Commercial and Industrial: 10/12/15ns
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One Chip Select plus one Output Enable pin
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Bidirectional data inputs and outputs directly
LVTTL-compatible
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Low power consumption via chip deselect
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Upper and Lower Byte Enable Pins
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Single 3.3V power supply
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Available in 44-pin, 400 mil plastic SOJ package and a 44-
pin, 400 mil TSOP Type II package and a 48 ball grid array,
9mm x 9mm package.
Description
The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized
as 256K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V416 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V416 are LVTTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a
44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x
9mm package.
Functional Block Diagram
Outp ut
Enab le
Buffer
Addres s
Buffe rs
Chip
Select
Buffer
Write
Enabl e
Buffer
Byte
Enable
Buffe rs
OE
A0 - A17
Row / Col umn
Decode rs
CS
WE
BHE
BLE
4, 194, 304 -b it
Memory
Array
Sens e
Amps
and
Write
Drivers
16
High
Byte
Outp ut
Buffer
High
Byte
Write
Buffer
Low
Byte
Write
Buffer
Low
Byte
Outp ut
Buffer
8
8
8
8
8
8
8
8
I/O 15
I/O 8
I/O 7
I/O 0
3624 drw 01
3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
IDT71V416S
IDT71V416L
6.422
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
*Pin 28 can either be a NC or connected to Vss
Top View
Pin Configurations - SOJ/TSOP
Pin Descriptions
SOJ Capacitance
(TA = +25°C, f = 1.0MHz)
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O 7
A9
A8
A7
A6
A5
WE
I/O 6
I/O 5
I/O 4
V
SS
V
DD
I/O 3
I/O 2
I/O 1
I/O 0
CS
A4
A3
A2
A1
A0
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A16
A15
OE
BHE
BLE
I/O 15
I/O 14
I/O 13
I/O 12
V
SS
V
DD
I/O 11
I/O 10
I/O 9
I/O 8
A14
A13
A12
A11
A10
A17
NC*
SO44-1
SO44-2
3624 drw 02
A
0
- A
17
Address Inputs Input
CS
Chip Select Input
WE
Write Enable Input
OE
Output Enable Input
BHE
High Byte Enable Input
BLE
Low Byte Enable Input
I/O
0
- I/O
15
Data Input/Output I/O
V
DD
3.3V Power Pwr
V
SS
Ground Gnd
3624 tbl 01
Symbol
Parameter
(1)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
7
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
8
pF
3624 tbl 02
1
2
3
4
5
6
A
BLE OE
A
0
A
1
A
2
NC
B
I/O
0
BHE
A
3
A
4
CS
I/O
8
C
I/O
1
I/O
2
A
5
A
6
I/O
10
I/O
9
D
V
SS
I/O
3
A
17
A
7
I/O
11
V
DD
E
V
DD
I/O
4
NC
A
16
I/O
12
V
SS
F
I/O
6
I/O
5
A
14
A
15
I/O
13
I/O
14
G
I/O
7
NC
A
12
A
13
WE
I/O
15
H
NC
A
8
A
9
A
10
A
11
NC
3624 tbl 11
Pin Configurations - 48 BGA
48 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
TBD
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
TBD
pF
3624 tbl 02b
6.42
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
3
Absolute Maximum Ratings
(1)
Recommended Operating
Temperature and Supply
Volta ge
Recommended DC Operating
Conditions
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
NOTES:
1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
Truth Table
(1)
NOTE:
1. H = VIH, L = VIL, X = Don't care.
Symbol
Rating
Value
Unit
V
DD
Supply Voltage Relative to V
SS
-0.5 to +4.6 V
V
IN,
V
OUT
Terminal Voltage Relative to
V
SS
-0.5 to V
DD
+0.5 V
T
BIAS
Temperature Under Bias -55 to +125
o
C
T
STG
Storage Temperature -55 to +125
o
C
P
T
Power Dissipation 1 W
I
OUT
DC Output Current 50 mA
3624 tbl 04
Grade
Temperature
V
SS
V
DD
Commercial
0
O
C to +70
O
C
0V
See Below
Industrial
–40
O
C to +85
O
C
0V
See Below
3624 tbl 05
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage 3.0 3.3 3.6 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage 2.0
____
V
DD
+0.3
(1 )
V
V
IL
Input Low Voltage
-0.3
(2)
____
0.8 V
3624 tbl 06
CS OE WE BLE BHE
I/O
0-
I/O
7
I/O
8-
I/O
15
Function
H X X X X High-Z High-Z Deselected - Standby
LLHLHDATA
OUT
High-Z Low Byte Read
L L H H L High-Z DATA
OUT
High Byte Read
LLHLLDATA
OUT
DATA
OUT
Word Read
LXLLL DATA
IN
DATA
IN
Word Write
LXLLH DATA
IN
High-Z Low Byte Write
L X L H L High-Z DATA
IN
High Byte Write
L H H X X High-Z High-Z Outputs Disabled
L X X H H High-Z High-Z Outputs Disabled
3624 tbl 03
P1-P3P4-P6P7-P9

IDT71V416L10Y8

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Description:
IC SRAM 4M PARALLEL 44SOJ
Lifecycle:
New from this manufacturer.
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