MAX9400/MAX9402/MAX9403/MAX9405
Detailed Description
The MAX9400/MAX9402/MAX9403/MAX9405 are
extremely fast, low-skew quad LVECL/ECL or LVPECL/
PECL buffer/receivers designed for high-speed data
and clock driver applications. The devices feature an
ultra-low propagation delay of 335ps and channel-to-
channel skew of 16ps in asynchronous mode with an
86mA supply current.
The four channels can be operated synchronously with
an external clock, or in asynchronous mode, determined
by the state of the SEL input. An enable input provides
the ability to force all the outputs to a differential low state.
A variety of input and output terminations are offered
for maximum design flexibility. The MAX9400 has open
inputs and open-emitter outputs. The MAX9402 has
open inputs and 50Ω series outputs. The MAX9403 has
100Ω differential input impedance and open-emitter
outputs. The MAX9405 has 100Ω differential input
impedance and 50Ω series outputs.
Supply Voltage
The MAX9400/MAX9402/MAX9403/MAX9405 are de-
signed for operation with a single supply. Using a single
negative supply of V
EE
= -2.375V to -5.5V (V
CC
= ground)
yields LVECL/ECL-compatible input and output levels.
Using a single positive supply of V
CC
= 2.375V to 5.5V
(V
EE
= ground) yields LVPECL/PECL input and output
levels.
Data Inputs
The MAX9400/MAX9402 have open inputs and require
external termination. The MAX9403/MAX9405 have inte-
grated 100Ω differential input termination resistors from
IN_ to IN_, reducing external component count.
Outputs
The MAX9402/MAX9405 have internal 50Ω series out-
put termination resistors and 8mA internal pulldown
current sources. Using integrated resistors reduces
external component count.
The MAX9400/MAX9403 have open-emitter outputs. An
external termination is required. See the Output
Termination section.
Enable
Setting EN = high and EN = low enables the device.
Setting EN = low and EN = high forces the outputs to a
differential low, and all changes on CLK, SEL, and IN_
are ignored.
Asynchronous Operation
Setting SEL = high and SEL = low enables the four
channels to operate independently as buffer/receivers.
The CLK signal is ignored in this mode. In asynchro-
nous mode, the CLK signal should be set to either a
logic low or high state to minimize noise coupling.
Synchronous Operation
Setting SEL = low and SEL = high enables all four
channels to operate in synchronous mode. In this
mode, buffered inputs are clocked into flip-flops simul-
taneously on the rising edge of the differential clock
input (CLK and CLK).
Differential Signal Input Limit
The maximum signal magnitude of the differential
inputs is V
CC
- V
EE
or 3V, whichever is less.
Applications Information
Input Bias
Unused inputs should be biased or driven as shown in
Figure 5. This avoids noise coupling that might cause
toggling at the unused outputs.
Output Termination
Terminate open-emitter outputs (MAX9400/MAX9403)
through 50Ω to V
CC
- 2V or use an equivalent Thevenin
termination. Terminate both outputs and use identical
termination on each for the lowest output-to-output
skew. When a single-ended signal is taken from a dif-
ferential output, terminate both outputs. For example, if
OUT_ is used as a single-ended output, terminate both
OUT_ and OUT_.
Ensure that the output currents do not exceed the cur-
rent limits as specified in the Absolute Maximum
Ratings table. Under all operating conditions, the
device’s total thermal limits should be observed.
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to
maximize the performance and noise immunity. Bypass
V
CC
to V
EE
with high-frequency surface-mount ceramic
0.1µF and 0.01µF capacitors as close to the device as
possible with the 0.01µF capacitor closest to the device
pins. Use multiple bypass vias for connection to mini-
mize inductance.
Circuit Board Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9400/MAX9402/MAX9403/MAX9405.
Connect each of the inputs and outputs to a 50Ω char-
acteristic impedance trace. Avoid discontinuities in dif-
ferential impedance and maximize common-mode
noise immunity by maintaining the distance between
differential traces and avoid sharp corners. Minimize
the number of vias to prevent impedance discontinu-
ities. Reduce reflections by maintaining the 50Ω char-
Quad Differential LVECL/LVPECL
Buffer/Receivers
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