6 Altera Corporation
Excalibur Device Overview
Two AMBA-compliant AHBs ensure that the embedded processor
activity is unaffected by peripheral and memory operation. Three
bidirectional AHB-to-AHB bridges enable embedded peripherals
and PLD-implemented peripherals to exchange data with the
embedded processor or with other peripherals.
The Excalibur family is supported by the following development
tools:
■ SOPC Builder from Altera
®
■ Quartus II from Altera
■ ADS, GNUPro and other third-party tools
Functional
Description
The Excalibur system architecture (embedded processor bus
structure, on-chip memory, and peripherals) combines the
performance advantages of ASIC integration with the flexibility and
time-to-market advantages of PLDs.
The Embedded Processor
The ARM922T is a member of the ARM9 family of processor cores.
Its Harvard architecture, implemented using a five-stage pipeline,
allows single clock-cycle instruction operation through
simultaneous fetch, decode, execute, memory, and write stages.
Figure 3 on page 7 shows the Excalibur embedded processor, the
ARM922T.
