AD536A Data Sheet
Rev. F | Page 12 of 15
C
AV
–V
S
V
IN
V
OUT
+V
S
14
13
12
11
10
9
8
1
2
3
4
5
6
7
–V
S
+V
S
AD536A
25k
25k
ABSOLUTE
VALUE
SQUARER/
DIVIDER
CURRENT
MIRROR
R4
50k
OFFSET
ADJUST
R3
750k
R2
365k
00504-007
BUF
NC
–V
S
C
AV
+V
S
NC
NC
NC
dB
COM
BUF OUT
R
L
BUF IN
I
OUT
SCALE
FACTOR
ADJUST
R1
500k
Figure 16. Optional External Gain and Output Offset Trims
SINGLE-SUPPLY OPERATION
Refer to Figure 17 for single supply-rail configurations between
5 V and 36 V. When powered from a single supply, the input
stage (VIN pin) is internally biased at a voltage between ground
and the supply, and the input signal ac coupled. Biasing the
device between the supply and ground is simply a matter of
connecting the COM pin to an external resistor divider and
bypassing to ground. The resistor values are large, minimizing
power consumption, as the COM pin current is only 5 μA.
Note that the 10 kΩ and 20 kΩ resistors connected to the COM pin
(Figure 17) are asymmetrical, that is, the voltage at the COM pin is
1/3 of the supply. This ratio of input bias to supply is optimum
for the precision rectifier (aka absolute value circuit) input
circuit employed for rectifying ac input waveforms and ensures
full input symmetry for low signal voltages.
Capacitor C2 is required for AC input coupling, however an
external dc return is unnecessary because biasing occurs
internally. SelectC2 for the desired low frequency breakpoint
using an input resistance of 16.7 kΩ for the 1/ωRC calculation;
C2 = 1 μF for a cutoff at 10 Hz. Figure 11 and Figure 12 show
the input and output signal ranges for dual and single supply
configurations, respectively. The load resistor, RL, provides a
path to sink output sink current when an input signal is
disconnected.
C
AV
V
IN
V
OUT
+V
S
14
13
12
11
10
9
8
1
2
3
4
5
6
7
AD536A
25k
ABSOLUTE
VALUE
SQUARER/
DIVIDER
CURRENT
MIRROR
C2
1µF
NONPOLARIZED
R
L
0.1µF
20k
10k
0.1µF
10k
TO
1k
00504-008
V
IN
NC
–V
S
C
AV
+V
S
NC
NC
NC
dB
COM
BUF OUT
R
L
BUF IN
I
OUT
BUF
Figure 17. Single-Supply Connection
CHOOSING THE AVERAGING TIME CONSTANT
The AD536A computes the rms of both ac and dc signals. If the
input is a slowly varying dc signal, the output of the AD536A
tracks the input exactly.
At higher frequencies, the average output of the AD536A
approaches the rms value of the input signal. The actual output
of the AD536A differs from the ideal output by a dc (or average)
error and some amount of ripple, as shown in Figure 18.
DC ERROR = E
O
– E
O
(IDEAL)
IDEAL E
O
DOUBLE FREQUENCY
RIPPLE
AVERAGE E
O
– E
O
E
O
TIME
00504-009
Figure 18. Typical Output Waveform for Sinusoidal Input
The dc error is dependent on the input signal frequency and
the value of C
AV
. Use Figure 19 to determine the minimum value
of C
AV
, which yields a given percentage of dc error above a given
frequency using the standard rms connection.
The ac component of the output signal is the ripple. There are
two ways to reduce the ripple. The first method involves using a
large value of C
AV
. Because the ripple is inversely proportional
to C
AV
, a tenfold increase in this capacitance affects a tenfold
reduction in ripple.
When measuring waveforms with high crest factors, such as low
duty cycle pulse trains, the averaging time constant should be at
least 10 times the signal period. For example, a 100 Hz pulse
rate requires a 100 ms time constant, which corresponds to a
4 μF capacitor (time constant = 25 ms per μF).
Data Sheet AD536A
The primary disadvantage in using a large C
AV
to remove ripple
is that the settling time for a step change in input level is
increased proportionately. Figure 19 illustrates that the
relationship between C
AV
and 1% settling time is 115 ms for
each microfarad of C
AV
. The settling time is twice as great for
decreasing signals as it is for increasing signals. The values in
Figure 19 are for decreasing signals. Settling time also increases
for low signal levels, as shown in Figure 20.
10 100 1k 10k
0.1
1
10
100
0.01
1 100k
INPUT FREQUENCY (Hz)
REQUIRED C
AV
(µF)
0.1
1
10
100
0.01
FOR 1% SETTLING TIME IN SECONDS
MULTIPLY READING BY 0.115
0.01% ERROR
0.1% ERROR
10% ERROR
1% ERROR
1
PERCENT DC ERROR AND PERCENT RIPPLE (PEAK)
VALUES FOR C
AV
AND
1% SETTLING TIME
FOR STATED % OF READING
AVERAGING ERROR
1
ACCURACY ± 20% DUE TO
COMPONENT TOLERANCE
00504-010
Figure 19. Error/Settling Time Graph for Use with the Standard RMS
Connection (See Figure 13 Through Figure 15)
10m 100m 1
7.5
10.0
5.0
1m
10
rms INPUT LEVE
L (V)
SETTLING TIME RELATIVE TO 1V rms
INPUT SETTLING TIME
1.0
2.5
00504-011
Figure 20. Settling Time vs. Input Level
A better method to reduce output ripple is the use of a postfilter.
Figure 21 shows a suggested circuit. If a single-pole filter is used
(C3 removed, R
X
shorted) and C2 is approximately twice the
value of C
AV
, the ripple is reduced, as shown in Figure 22, and
settling time is increased. For example, with C
AV
= 1 µF and C2
= 2.2 μF, the ripple for a 60 Hz input is reduced from 10% of
reading to approximately 0.3% of reading.
The settling time, however, is increased by approximately a
factor of 3. Therefore, the values of C
AV
and C2 can be reduced
to permit faster settling times while still providing substantial
ripple reduction.
The two-pole postfilter uses an active filter stage to provide
even greater ripple reduction without substantially increasing
the settling times over a circuit with a one-pole filter. The values
of C
AV
, C2, and C3 can then be reduced to allow extremely fast
settling times for a constant amount of ripple. Caution should
be exercised in choosing the value of C
AV
, because the dc error
is dependent on this value and is independent of the postfilter.
For a more detailed explanation of these topics, refer to the RMS to
DC Conversion Application Guide, 2nd Edition.
C2
V
IN
C
AV
+V
S
14
13
12
11
10
9
8
1
2
3
4
5
6
7
AD536A
25kΩ
ABSOLUTE
VALUE
SQUARER/
DIVIDER
CURRENT
MIRROR
–V
S
Rx
24kΩ
+
+
C3
1
V
rms
OUT
1
FOR SINGLE POLE, SHORT Rx, REMOVE C3.
00504-012
V
IN
NC
–V
S
C
AV
+V
S
NC
NC
NC
dB
COM
BUF OUT
R
L
BUF IN
I
OUT
BUF
Figure 21. Two-Pole Postfilter
1
1k100
10k
0.1
10
10
DC ERROR OR RIPPLE (% of Reading)
PEAK-TO-PEAK RIPPLE
C
AV
= 1µF
DC ERROR
C
AV
= 1µF
(ALL FILTERS)
PEAK-TO-PEAK RIPPLE
C
AV
= 1µF
C2 = C3 = 2.2µF (TWO-POLE)
00504-013
Rx = 0Ω
PEAK-TO-PEAK
RIPPLE (ONE POLE)
C
AV
= 1µF, C2 = 2.2µF
FREQUENCY (Hz)
Figure 22. Performance Features of Various Filter Types
(See Figure 13 to Figure 15 for Standard RMS Connection)
Rev. F | Page 13 of 15
AD536A
Data Sheet
OUTLINE DIMENSIONS
\
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
14
1
7
8
0.310 (7.87)
0.220 (5.59)
PIN 1
0.080 (2.03) MAX
0.005 (0.13) MIN
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.070 (1.78)
0.030 (0.76)
0.100 (2.54)
BSC
0.150
(3.81)
MIN
0.765 (19.43) MAX
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
Figure 23. 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-14)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1
20
4
9
8
13
19
14
3
18
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
45° TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.100 (2.54) REF
0.200 (5.08)
REF
0.150 (3.81)
BSC
0.075 (1.91)
REF
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
022106-A
Figure 24. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13) MIN
0.098 (2.49) MAX
0.100 (2.54) BSC
15°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.785 (19.94) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
PIN 1
1
7
8
14
Figure 25. 14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Dimensions shown in inches and (millimeters)
Rev. F | Page 14 of 15

AD536AJDZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized RMS/DC CONVERTER IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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