www.fairchildsemi.com 4
FIN1049
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 5: All typical values are at T
A
= 25°C and with V
CC
= 3.3V.
Note 6: t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same
direction.
Note 7: t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 8: f
MAX
generator input conditions: t
r
= t
f
< 1ns (10% to 90%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45% / 55%, V
OD
> 250mV, all chan-
nels switch.
Note 9: f
MAXT
generator input conditions: t
r
= t
f
< 1ns (10% to 90%), 50% duty cycle, V
ID
= 200mV, V
CM
= 1.2V. Output criteria: duty cycle = 45% / 55%, V
OH
> 2.7V. V
OL
< 0.25V, all channels switching.
Symbol Parameter Test Conditions
Min Typ Max
Units
(Note 5)
Switching Characteristics - LVDS Outputs
t
PLHD
Differential Propagation Delay LOW-to-HIGH
See Figures 3, 4
2.0 ns
t
PHLD
Differential Propagation Delay HIGH-to-LOW 2.0 ns
t
TLHD
Differential Output Rise Time (20% to 80%) 0.2 1.0 ns
t
THLD
Differential Output Fall Time (80% to 20%) 0.2 1.0 ns
t
SK(P)
Pulse Skew |t
PLH
- t
PHL
| 0.35 ns
t
SK(LH)
, Channel-to-Channel Skew (Note 6)
0.35 ns
t
SK(HL)
t
SK(PP)
Part-to-Part Skew (Note 7) 1.0 ns
t
PZHD
Differential Output Enable Time from Z-to-HIGH
See Figures 5, 6
6.0 ns
t
PZLD
Differential Output Enable Time from A-to-LOW 6.0 ns
t
PHZD
Differential Output Disable Time from HIGH-to-Z 3.0 ns
t
PLZD
Differential Output Disable Time from LOW-to-Z 3.0 ns
f
MAXD
Maximum Frequency (Note 8) See Figure 3 200 MHz
Switching Characteristics - LVTTL Outputs
t
PHL
Propagation Delay HIGH-to-LOW Measured from 20% to 80% signal 0.5 1.0 3.5 ns
t
PLH
Propagation Delay LOW-to-HIGH V
ID
= 200mV; 0.5 1.0 3.5 ns
t
SK1
Pulse Skew Distributed Load 0.0 35.0 400 ps
t
SK2
Channel-to-Channel Skew C
L
= 15pF and 50; 0.0 50.0 500 ps
t
SK3
Part-to-Part Skew R
L
= 1K; 0.0 1.0 ns
t
LHR
Transition Time LOW-to-HIGH V
OS
= 1.2V; 0.1 0.25 1.4 ns
t
HLR
Transition Time HIGH-to-LOW See Figures 7, 8 0.1 0.18 1.4 ns
t
PHZ
Disable Time HIGH-to-Z
See Figures 9, 10
2.2 4.5 8.0 ns
t
PLZ
Disable Time LOW-to-Z 1.3 3.5 8.0 ns
t
PZH
Enable Time Z-to-HIGH 1.8 3.0 7.0 ns
t
PZL
Enable Time Z-to-LOW 0.9 1.4 7.0 ns
f
MAXT
Maximum Frequency (Note 9) See Figure 7 200 MHz
5 www.fairchildsemi.com
FIN1049
Required Specifications
1. Human Body Model ESD and Machine Model ESD
should be measured using MIL-STD-883C method
3015.7 standard.
2. Latch-up immunity should be tested to the EIA/JEDEC
Standard Number 78 (EIA/JESD78).
Note: C
L
= 15pF, includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Note: R
L
= 100
FIGURE 2. LVDS Output Circuit for DC Test
Applied Voltages (V)
Resulting Differential Input Resulting Common
Voltage (mV) Mode Input Voltage (V)
V
IA
V
IB
V
ID
V
IC
1.25 1.15 100 1.2
1.15 1.25
100 1.2
V
CC
V
CC
- 0.1 100 V
CC
- 0.05
V
CC
- 0.1 V
CC
100 V
CC
- 0.05
0.1 0.0 100 0.05
0.0 0.1
100 0.05
1.75 0.65 1100 1.2
0.65 1.75
1100 1.2
V
CC
V
CC
- 1.1 1100 V
CC
- 0.55
V
CC
- 1.1 V
CC
1100 V
CC
- 0.55
1.1 0.0 1100 0.55
0.0 1.1
1100 0.55
www.fairchildsemi.com 6
FIN1049
Required Specifications (Continued)
Note A: R
L
= 100
Note B: Z
O
= 50 and C
T
= 15 pF Distributed
FIGURE 3. LVDS Output Propagation Delay and Transition Time Test Circuit
FIGURE 4. LVTTL Input to LVDS Output AC Waveform

FIN1049MTC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Buffers & Line Drivers LVDS Driver/Receiver Dual Line
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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