MC74VHC574DWR2G

MC74VHC574
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS
Unit
T
A
= 40 to 85°CT
A
= 25°C
V
CC
V
Test ConditionsParameterSymbol Unit
MaxMinMaxTypMin
V
CC
V
Test ConditionsParameterSymbol
I
in
Maximum Input
Leakage Current
V
in
= 5.5V or GND 0 to 5.5 ± 0.1 ± 1.0 μA
I
OZ
Maximum
ThreeState Leakage
Current
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
5.5 ± 0.25 ± 2.5 μA
I
CC
Maximum Quiescent
Supply Current
V
in
= V
CC
or GND 5.5 4.0 40.0 μA
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbol Parameter Test Conditions
T
A
= 25°C T
A
= 40 to 85°C
Unit
Min Typ Max Min Max
f
max
Maximum Clock Frequency
(50% Duty Cycle)
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
80
50
125
75
65
45
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
130
85
180
115
110
75
t
PLH
,
t
PHL
Maximum Propagation Delay,
CP to Q
V
CC
= 3.3 ± 0.3 C
L
= 15pF
C
L
= 50pF
8.5
11.0
13.2
16.7
1.0
1.0
15.5
19.0
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
5.6
7.1
8.6
10.6
1.0
1.0
10.0
12.0
t
PZL
,
t
PZH
Output Enable Time,
OE
to Q
V
CC
= 3.3 ± 0.3V C
L
= 15pF
R
L
= 1kΩ C
L
= 50pF
8.2
10.7
12.8
16.3
1.0
1.0
15.0
18.5
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
R
L
= 1kΩ C
L
= 50pF
5.9
7.4
9.0
11.0
1.0
1.0
10.5
12.5
t
PLZ
,
t
PHZ
Output Disable Time,
OE
to Q
V
CC
= 3.3 ± 0.3V C
L
= 50pF
R
L
= 1kΩ
11.0 15.0 1.0 17.0
ns
V
CC
= 5.0 ± 0.5V C
L
= 50pF
R
L
= 1kΩ
7.1 10.1 1.0 11.5
t
OSLH
,
t
OSHL
Output to Output Skew
V
CC
= 3.3 ± 0.3V C
L
= 50pF
(Note 1)
1.5 1.5 ns
V
CC
= 5.0 ± 0.5V C
L
= 50pF
(Note 1)
1.0 1.0 ns
C
in
Maximum Input Capacitance 4 10 10 pF
C
out
Maximum ThreeState Output
Capacitance, Output in
HighImpedance State
6 pF
C
PD
Power Dissipation Capacitance (Note 2)
Typical @ 25°C, V
CC
= 5.0V
pF
28
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
t
PLHn
|, t
OSHL
= |t
PHLm
t
PHLn
|.
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/ 8 (per flipflop). C
PD
is used to determine the
noload dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
MC74VHC574
http://onsemi.com
5
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 5.0V)
Symbol
Parameter
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.9 1.2 V
V
OLV
Quiet Output Minimum Dynamic V
OL
0.9 1.2 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
TIMING REQUIREMENTS (Input t
r
= t
f
= 3.0ns)
Symbol
Parameter Test Conditions
T
A
= 25°C
T
A
= 40
to 85°C
Unit
Typ Limit Limit
t
su
Minimum Setup Time, D to CP V
CC
= 3.3 ± 0.3 V
V
CC
= 5.0 ± 0.5 V
3.5
3.5
3.5
3.5
ns
t
h
Minimum Hold Time, CP to D V
CC
= 3.3 ± 0.3 V
V
CC
= 5.0 ± 0.5 V
1.5
1.5
1.5
1.5
ns
t
w
Minimum Pulse Width, CP V
CC
= 3.3 ± 0.3 V
V
CC
= 5.0 ± 0.5 V
5.0
5.0
5.5
5.0
ns
Figure 3. Switching Waveforms
CP
Q
V
CC
GND
50%
50% V
CC
t
PLH
t
PHL
t
w
1/f
max
Q
Q
50%
50% V
CC
t
PZL
t
PLZ
t
PZH
t
PHZ
V
CC
GND
HIGH
IMPEDANCE
V
OL
+0.3V
V
OH
-0.3V
HIGH
IMPEDANCE
OE
50% V
CC
Figure 4. Figure 5.
50%CP
V
CC
VALID
GND
V
CC
GND
t
su
t
h
50%D
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
MC74VHC574
http://onsemi.com
6
Figure 6. Expanded Logic Diagram
C
D
Q
2
D0
19
Q0
C
D
Q
3
D1
18
Q1
C
D
Q
4
D2
17
Q2
C
D
Q
5
D3
16
Q3
C
D
Q
6
D4
15
Q4
C
D
Q
7
D5
14
Q5
C
D
Q
8
D6
13
Q6
C
D
Q
9
D7
12
Q7
11
CP
1
OE
Figure 7. Test Circuit
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
1 kΩ
Figure 8. INPUT EQUIVALENT CIRCUIT
INPUT

MC74VHC574DWR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops 2-5.5V CMOS Octal D-Type w/3-State Out
Lifecycle:
New from this manufacturer.
Delivery:
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