Data Sheet ADuCM362/ADuCM363
Rev. 0 | Page 13 of 24
External Reference (2.5 V)
Table 6 through Table 9 provide rms noise specifications for ADC0 and ADC1 using the external reference (2.5 V). Table 6 and Table 7 list
the rms noise for both ADCs with various gain and output update rate values. Table 8 and Table 9 list the typical output rms noise effective
ENOB in normal mode for both ADCs with various gain and output update rate values. (Peak-to-peak ENOB is shown in parentheses.)
Table 6. RMS Noise vs. Gain and Output Update Rate, External Reference (2.5 V), Gain = 1, 2, 4, 8, and 16
Update
Rate (Hz)
Chop/Sinc
ADCFLT
Register
Value
RMS Noise (μV)
Gain = 1, ±V
REF
,
ADCxMDE =
0x01
Gain = 2,
±500 mV,
ADCxMDE =
0x11
Gain = 4,
±250 mV,
ADCxMDE =
0x21
Gain = 8,
±125 mV,
ADCxMDE =
0x31
Gain = 16,
±62.5 mV,
ADCxMDE =
0x41
3.53 On/sinc3 0x8E7C 1.1 0.5 0.27 0.17 0.088
30 Off/sinc3 0x007E 3 1.4 0.85 0.44 0.27
50 Off/sinc3 0x007D 3.9 2.2 0.92 0.46 0.3
100 Off/sinc3 0x004D 5.2 2.8 1.25 0.63 0.38
488 Off/sinc4 0x100F 9.3 5.0 2.5 1.2 0.75
976 Off/sinc4 0x1007 12.5 7 3.5 1.75 1.2
1953 Off/sinc4 0x1003 20.0 10 5.7 2.6 1.71
3906 Off/sinc4 0x1001 140.0 70.0 35.0 17.2 8.9
Table 7. RMS Noise vs. Gain and Output Update Rate, External Reference (2.5 V), Gain = 32, 64, and 128
Update
Rate (Hz)
Chop/
Sinc
RMS Noise (μV)
ADCFLT
Register
Value
Gain = 32,
1
±62.5 mV,
ADCxMDE =
0x49
Gain = 32,
1, 2
±22.18 mV,
ADCxMDE =
0x51
Gain = 64,
3
±15.625 mV,
ADCxMDE =
0x59
Gain = 64,
3, 4
±10.3125 mV,
ADCxMDE =
0x61
Gain = 128,
5
±7.8125 mV,
ADCxMDE =
0x69
Gain = 128,
5, 6
±3.98 mV,
ADCxMDE =
0x71
3.53 On/sinc3 0x8E7C 0.076 0.07 0.088 0.06 0.068 0.58
30 Off/sinc3 0x007E 0.21 0.22 0.21 0.19 0.175 0.17
50 Off/sinc3 0x007D 0.265 0.21 0.27 0.2 0.225 0.19
100 Off/sinc3 0x004D 0.37 0.32 0.366 0.28 0.32 0.26
488 Off/sinc4 0x100F 0.73 0.7 0.73 0.57 0.64 0.5
976 Off/sinc4 0x1007 1.1 0.83 1.01 0.77 0.89 0.75
1953 Off/sinc4 0x1003 2.05 1.3 1.6 1.24 1.3 1.1
3906 Off/sinc4 0x1001 9.4 4.8 5.1 2.65 3.2 1.88
1
ADCxMDE = 0x49 sets the PGA for a gain of 16 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x51 sets the PGA for a gain of 32 with the modulator gain off. ADCxMDE = 0x49 has slightly higher noise but supports a wider input range.
2
If AVDD < 2.0 V and ADCxMDE = 0x51, the input range is ±17.5 mV.
3
ADCxMDE = 0x59 sets the PGA for a gain of 32 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x61 sets the PGA for a gain of 64 with the modulator gain off. ADCxMDE = 0x59 has slightly higher noise but supports a wider input range.
4
If AVDD < 2.0 V and ADCxMDE = 0x61, the input range is ±8.715 mV.
5
ADCxMDE = 0x69 sets the PGA for a gain of 64 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x71 sets the PGA for a gain of 128 with the modulator gain off. ADCxMDE = 0x69 has slightly higher noise but supports a wider input range.
6
If AVDD < 2.0 V and ADCxMDE = 0x71, the input range is ±3.828 mV.