74LVQ574
4/13
Table 7: Dynamic Switching Characteristics
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Table 8: AC Electrical Characteristics (C
L
= 50 pF, R
L
= 500 , Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ±
0.3V
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.5 0.8
V
V
OLV
-0.8 -0.6
V
IHD
Dynamic High
Voltage Input
(note 1, 3)
3.3 2 V
V
ILD
Dynamic Low
Voltage Input
(note 1, 3)
3.3 0.8 V
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Q
2.7 7.4 12.0 14.0 16.0
ns
3.3
(*)
6.1 9.0 10.5 12.0
t
PLZ
t
PHZ
Output Enable
Time
2.7 8.0 12.0 14.0 16.0
ns
3.3
(*)
6.5 9.0 10.5 12.0
t
PZL
t
PZH
Output Disable
Time
2.7 8.0 12.0 14.0 16.0
ns
3.3
(*)
6.5 9.0 10.5 12.0
t
W
CK Pulse Width
HIGH or LOW
2.7 4.0 2.0 4.0 4.0
ns
3.3
(*)
3.0 1.5 3.0 3.0
t
sL
t
sH
Setup Time D to
CK, HIGH or LOW
2.7 3.0 0.0 3.0 3.0
ns
3.3
(*)
2.0 0.0 2.0 2.0
t
hL
t
hH
Hold Time CK to D,
HIGH or LOW
2.7 1.0 0.0 1.0 1.0
ns
3.3
(*)
1.5 0.0 1.5 1.5
f
MAX
Maximum Clock
Frequency
2.7 100 150 80 60
MHz
3.3
(*)
120 180 100 80
t
OSLH
t
OSHL
Output To Output
Skew Time
(note1, 2)
2.7 0.5 1.0 1.0 1.0
ns
3.3
(*)
0.5 1.0 1.0 1.0
74LVQ574
5/13
Table 9: Capacitive Characteristics
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per Flip
Flop)
Figure 4: Test Circuit
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500 or equivalent
R
T
= Z
OUT
of pulse generator (typically 50)
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
C
IN
Input Capacitance
3.3 4 pF
C
OUT
Output
Capacitance
3.3 7 pF
C
PD
Power Dissipation
Capacitance
(note 1)
3.3
f
IN
= 10MHz
15 pF
TEST SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
2V
CC
t
PZH
, t
PHZ
Open
74LVQ574
6/13
Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)
Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)

74LVQ574MTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Flip Flops Octal "D" Flip-Flop
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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