21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
TM
32,768 x 18 and 65,536 x 18
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285.
In FWFT mode: D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
3.
t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
PAF
). If the time between the rising edge of
RCLK and the rising edge of WCLK is less than t
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAF
RCLK
(3)
t
PAF
REN
4512 drw 19
t
ENS
t
ENH
t
ENS
D - (m+1) words in FIFO
(2)
t
PAF
D - m words in FIFO
(2)
t
SKEW2
1
2
12
D-(m+1) words
in FIFO
(2)
RCLK
LD
REN
Q
0
- Q
15
tLDH
tLDS
tENS
DATA IN OUTPUT
REGISTER
PAE
OFFSET
PAF
OFFSET
tENH
tENH
tLDH
4512 drw 18
t
CLK
tA
tA
tCLKH
tCLKL
WCLK
LD
WEN
D
0
- D
15
4512 drw 17
t
LDS
t
ENS
PAE
OFFSET
PAF
OFFSET
t
DS
t
DH
t
LDH
t
ENH
t
CLK
t
LDH
t
ENH
t
DH
t
CLKH
t
CLKL