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HC9P5504B-5ZX96

P1-P3P4-P6P7-P9
7
Schematic Diagram
SLIC FUNCTIONAL SCHEMATIC
Pin Numbers for SOIC Package
V
B2
V
B1
V
B2
V
B3
V
B4
V
B5
+5V
I
B1
I
B2
I
B3
I
B4
I
B5
I
B6
I
B7
I
B8
V
BAT
I
B9
I
B10
I
B11
V
B
+
V
B
+
A-100
TRANSV’L
I/V AMP
-
+
I
B6
R
6
R
5
R
11
V
B
+
R
7
R
8
R
10
R
9
R
22
R
23
R
3
R
4
R
1
R
2
R
16
R
15
V
BAT
V
BAT
R
12
V
BAT
V
B
+
A-200
LONG’L
I/V AMP
I
B7
-
+
R
20
V
BAT
V
B
+
A-400
TIP FEED
AMP
I
B4
-
+
RING
FEED
SENSE
V
BAT
V
BAT
5V
V
B4
I
B8
RING TRIP DETECTOR
+
SWITCH HOOK
V
B1
I
B6
+
R
18
DETECTOR
V
B
+
Q
D28
Q
D27
V
BAT
- +
-
GND SHORTS
CURRENT
LIMITING
I
B1
V
B3
THERMAL
LIMITING
V
B5
STTL
AND LOGIC
INTERFACE
RFC
SH
GK
V
B5
-
+
I
B2
LOAD CURRENT
LIMITING
R
14
R
13
V
BAT
V
BAT/2
REFERENCE
R
21
V
BAT
A-300
RING FEED
AMP
I
B5
-
+
RING
RF
TIP
TF
10
2
3
1
9
RX C4 V
BAT
BAT ANA DIG
V
B
+
GND GND GND
21 22 11 12 23 6 4
+ -
OUT
20 19 18
V
BAT
I
B3
V
B
+
V
B
+
5V
I
B10
V
BAT
PD
15
RC
SHD
GKD
C2
16
13
17
14
TXC3 RS RD
87245
R
17
V
B2
V
B
+
R
19
V
BAT
Q
D3
Q
D36
VOLTAGE AND CURRENT
BIAS NETWORK
A-500
OP AMP
HC-5504B
8
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Overvoltage Protection and Longitudinal
Current Protection
The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
High voltage surge conditions are as specified in Table 1.
The SLIC will withstand longitudinal currents up to a
maximum or 30mA
RMS
, 15mA
RMS
per leg, without any
performance degradation.
LOGIC GATE SCHEMATIC
Schematic Diagram (Continued)
15
5
6
12
4
16
13
A
B
C
C
B
A
TTL
TO
STTL
TTL
TO
STTL
TTL
TO
STTL
TO
R
21
GKDSHDRDPDRCRS
C2
TTL
TO
STTL
TTL
TO
STTL
DELAY
LOGIC BIAS
RELAY
DRIVER
SH
GK
11 14
3
97
8
10
2
1
SCHOTTKY LOGIC
TABLE 1.
PARAMETER
TEST
CONDITION
PERFORMANCE
(MAX) UNITS
Longitudinal
Surge
10µs Rise/ ±1000 (Plastic) V
PEAK
1000µs Fall ±500 (Ceramic) V
PEAK
Metallic Surge 10µs Rise/ ±1000 (Plastic) V
PEAK
1000µs Fall ±500 (Ceramic) V
PEAK
T/GND 10µs Rise/ ±1000 (Plastic) V
PEAK
R/GND 1000µs Fall ±500 (Ceramic) V
PEAK
50/60Hz Current
T/GND 11 Cycles 700 (Plastic) V
RMS
R/GND Limited to
10A
RMS
350 (Ceramic) V
RMS
HC-5504B
9
Applications Diagram
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
Typical Component Values
C
2
= 0.15µF, 10V.
C
3
= 0.3µF, 30V.
C
4
= 0.5µF to 1.0µF, 10%, 20V (Should be nonpolarized).
C
5
= 0.5µF, 20V.
C
6
= C
7
= 0.5µF (10% Match Required) (Note 7).
C
8
= 0.01µF, 100V.
C
9
= 0.01µF, 20V, ±20%.
R
1
= R
2
= R
3
= 100kΩ (0.1% Match Required, 1% absolute
value) ZB = 0 for 600Ω Terminations (Note 7).
R
B1
= R
B2
= R
B3
= R
B4
= 150Ω (0.1% Match Required, 1%
absolute value).
R
S1
= R
S2
=1kΩ, typically.
C
S1
= C
S2
= 0.1µF, 200V typically, depending on V
RING
and line length.
Z
1
= 150V to 200V transient protection.
PTC used as ring generator ballast.
NOTES:
5. Secondary protection diode bridge recommended is a 2A, 200V type.
6. To obtain the specified transhybrid loss it is necessary for the three legs of the balance network, C
6
-R
1
and R
2
and C
7
-ZB-R
3
, to match in
impedance to within 0.3%. Thus, if C
6
and C
7
are 1µF each, a 20% match is adequate. It should be noted that the transmit output to C
6
sees
a -22V step when the loop is closed. Too large a value for C
6
may produce an excessively long transient at the op amp output to the PCM
Filter/CODEC.
A 0.5µF and 100kΩ gives a time constant of 50ms. The uncommitted op amp output is internally clamped to stay within ±6.6V and is current
limited.
7. All grounds (AG, BG, and DG) must be applied before V
B
+ or V
B
-. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
8. Application shows Ring Injected Ringing, Balanced or Tip injected configuration may be used.
9. Pin numbers given for SOIC package.
R
B4
K
1B
K
1A
RING
RING FEED
RING FEED SENSE
TIP
V
B
-
SLIC
HC-5504B
R
S1
R
B2
R
B1
PTC
Z
1
-48V
150V
PEAK
(MAX)
RING GENERATOR
RING
R
B3
R
S2
C
S2
SUBSCRIBER
LOOP
-48V
SYSTEM CONTROLLER
K
1
8
1
9
10
3
2
1
TIP FEED
TIP
RD
OP AMP
RX
TX
+IN
-IN
OUT
C2
C3
C4
NEG.
BATT.
BATT.
GND.
DIG.
GND.
ANA.
GND. V
B
+
POWER
DENIAL
SWITCH
HOOK
DETECT
GROUND
KEY
DETECT
RING
SYNC
RING
CMD
15 13 14 7 16
11 12 6 23
C
9
4
V
B
+
C
8
C
4
C
3
C
2
+
+
21
24
20
19
18
17
5
22
C
6
R
1
R
2
C
7
C
5
R
3
BALANCE NETWORK
PCM
FILTER/
CODEC
SWITCHING
NETWORK
ZB
5V TO
12V
PRIMARY
PROTECTION
C
S1
HC-5504B
P1-P3P4-P6P7-P9

HC9P5504B-5ZX96

Mfr. #:
Buy HC9P5504B-5ZX96
Manufacturer:
Renesas / Intersil
Description:
Telecom Interface ICs HC9P5504B-5EL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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