MC14018BCP

MC14018B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic Symbol
V
DD
Vdc
All Types
Unit
Min Typ
(Note 6)
Max
Output Rise and Fall Time
t
TLH
, t
THL
= (1.35 ns/pF) C
L
+ 32 ns
t
TLH
, t
THL
= (0.6 ns/pF) C
L
+ 20 ns
t
TLH
, t
THL
= (0.4 ns/pF) C
L
+ 20 ns
t
TLH
, t
THL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q
t
PLH
, t
PHL
= (0.90 ns/pF) C
L
+ 265 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C
L
+ 102 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C
L
+ 72 ns
t
PLH
,
t
PHL
5.0
10
15
310
120
85
620
240
170
ns
Reset to Q
t
PLH
= (0.90 ns/pF) C
L
+ 325 ns
t
PLH
= (0.36 ns/pF) C
L
+ 132 ns
t
PLH
= (0.26 ns/pF) C
L
+ 81 ns
5.0
10
15
370
150
100
740
300
200
ns
Preset Enable to Q
t
PLH
, t
PHL
= (0.90 ns/pF) C
L
+ 325 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C
L
+ 132 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C
L
+ 81 ns
5.0
10
15
370
150
100
740
300
200
ns
Setup Time
Data (Pin 1) to Clock
t
su
5.0
10
15
200
100
80
0
0
0
ns
Jam Inputs to Preset Enable 5.0
10
15
200
100
80
0
0
0
ns
Data (Jam Inputs)−to−Preset
Enable Hold Time
t
h
5.0
10
15
540
500
480
270
250
240
ns
Clock Pulse Width t
WH
5.0
10
15
400
200
160
200
100
80
ns
Reset or Preset Enable
Pulse Width
t
WH
5.0
10
15
290
130
110
145
65
55
ns
Clock Rise and Fall Time t
TLH
, t
THL
5.0
10
15
No Limit
ns
Clock Pulse Frequency f
cl
5.0
10
15
2.5
6.5
8.0
1.25
3.25
4.0
MHz
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Switching Time Waveforms
ANY INPUT
ANY OUTPUT
20 ns 20 ns
90%
50%
10%
V
DD
V
SS
V
OH
V
OL
t
PLH
t
PHL
t
TLH
t
THL
90%
50%
10%
MC14018B
http://onsemi.com
5
TIMING DIAGRAM
(Q
5 Connected to Data Input)
CLOCK
RESET
PRESET ENABLE
JAM 1
JAM 2
JAM 3
JAM 4
JAM 5
Q1
Q2
Q3
Q4
Q5
DON’T CARE
UNTIL PRESET ENABLE
GOES HIGH
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
LOGIC DIAGRAM
JAM 1 JAM 2 JAM 3 JAM 4 JAM 5
129732
CLOCK14
DATA1
RESET15
PRESET ENABLE10
CLOCK
SHAPER
54 61113
Q1Q2Q3Q4Q5
SS SSS
DD DDD
CC CCC
QQ QQQ
RP RP RP RP R P
Q
V
DD
= PIN 16
V
SS
= PIN 8
FUNCTION SELECTION
Counter
Mode
Connect
Data Input
(Pin 1) to:
Comments
Divide by 10
Divide by 8
Divide by 6
Divide by 4
Divide by 2
Q5
Q4
Q3
Q2
Q1
No external
components needed.
Divide by 9
Divide by 7
Divide by 5
Divide by 3
Q5 Q4
Q4 Q3
Q3 Q2
Q2 Q1
Gate package needed
to provide AND
function. Counter
Skips all 1’s state
MC14018B
http://onsemi.com
6
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____

MC14018BCP

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers LOG CMOS COUNTER DIVIDE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet