© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 6
1 Publication Order Number:
MC14018B/D
MC14018B
Presettable Divide−By−N
Counter
The MC14018B contains five Johnson counter stages which are
asynchronously presettable and resettable. The counters are
synchronous, and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input.
Data on the Jam inputs will then be transferred to their respective Q
outputs (inverted). A logic 1 on the reset input will cause all Q outputs
to go to a logic 1 state.
Division by any number from 2 to 10 can be accomplished by
connecting appropriate Q outputs to the data input, as shown in the
Function Selection table. Anti−lock gating is included in the
MC14018B to assure proper counting sequence.
Features
• Fully Static Operation
• Schmitt Trigger on Clock Input
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Pin−for−Pin Replacement for CD4018B
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage Range −0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
± 10 mA
P
D
Power Dissipation, per Package
(Note 1)
500 mW
T
A
Ambient Temperature Range −55 to +125 °C
T
stg
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature
(8−Second Soldering)
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (V
in
or V
out
) v V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
MC14018BCP
AWLYYWWG
SOIC−16
D SUFFIX
CASE 751B
14018BG
AWLYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Indicator
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
16
1
1
16
