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AT29C512-12JC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
4
AT29C512
0456F–FLASH–12/02
DATA POLLING: The AT29C512 features DATA polling to indicate the end of a program
cycle. During a program cycle an attempted read of the last byte loaded will result in the com-
plement of the loaded data on I/O7. Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during
the program cycle.
TOGGLE BIT: In addition to DATA
polling the AT29C512 provides another method for deter-
mining the end of a program or erase cycle. During a program or erase operation, successive
attempts to read data from the device will result in I/O6 toggling between one and zero. Once
the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examin-
ing the toggle bit may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte soft-
ware code. Please see Software Chip Erase application note for details.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°Cto+125°C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65°Cto+150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
5
AT29C512
0456F–FLASH–12/02
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V ± 0.5V.
4. Manufacturer Code: 1F, Device Code: 5D.
5. See details under Software Product Identification Entry/Exit.
DC and AC Operating Range
AT29C512-70 AT29C512-90 AT29C512-12 AT29C512-15
Operating
Temperature (Case)
Com. 0°C-70°C0°C-70°C
0°C-70°C 0°C-70°C
Ind. -40°C-85°C-40°C-85°C
-40°C-85°C -40°C-85°C
V
CC
Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10%
Note:
Not recommended for New Designs.
Operating Modes
Mode CE OE WE Ai I/O
Read V
IL
V
IL
V
IH
Ai D
OUT
Program
(2)
V
IL
V
IH
V
IL
Ai D
IN
5V Chip Erase V
IL
V
IH
V
IL
Ai
Standby/Write Inhibit V
IH
X
(1)
XXHighZ
Program Inhibit X X V
IH
Program Inhibit X V
IL
X
Output Disable X V
IH
XHighZ
Product Identification
Hardware V
IL
V
IL
V
IH
A1 - A15 = V
IL
,A9=V
H
,
(3)
A0 = V
IL
Manufacturer Code
(4)
A1-A15 = V
IL
,A9=V
H
,
(3)
A0 = V
IH
Device Code
(4)
Software
(5)
A0 = V
IL
Manufacturer Code
(4)
A0 = V
IH
Device Code
(4)
DC Characteristics
Symbol Parameter Condition Min Max Units
I
LI
Input Load Current V
IN
=0VtoV
CC
10 µA
I
LO
Output Leakage Current V
I/O
=0VtoV
CC
10 µA
I
SB1
V
CC
Standby Current CMOS CE =V
CC
-0.3VtoV
CC
Com. 100 µA
Ind. 300 µA
I
SB2
V
CC
Standby Current TTL CE =2.0VtoV
CC
3mA
I
CC
V
CC
Active Current f = 5 MHz; I
OUT
= 0 mA 50 mA
V
IL
Input Low Voltage 0.8 V
V
IH
Input High Voltage 2.0 V
V
OL
Output Low Voltage I
OL
=2.1mA 0.45 V
V
OH1
Output High Voltage I
OH
=-400µA2.4V
V
OH2
Output High Voltage CMOS I
OH
=-100µA; V
CC
=4.5V 4.2 V
6
AT29C512
0456F–FLASH–12/02
AC Read Waveforms
(1)(2)(3)(4)
Notes: 1. CE may be delayed up to t
ACC
-t
CE
after the address transition without impact on t
ACC
.
2. OE
may be delayed up to t
CE
-t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
-t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol Parameter
AT29C512-70 AT29C512-90
AT29C512-12 AT29C512-15
UnitsMin Max Min Max
Min Max Min Max
t
ACC
Address to Output Delay 70 90 120 150 ns
t
CE
(1)
CE to Output Delay 70 90 120 150 ns
t
OE
(2)
OE to Output Delay 0 35 0 40 0 50 0 70 ns
t
DF
(3)(4)
CE or OE to Output Float 0 10 0 25 0 30 0 40 ns
t
OH
Output Hold from OE,CEor
Address, whichever
occurred first
00
0 0 ns
Note:
Not recommended for New Designs.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

AT29C512-12JC

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IC FLASH 512K PARALLEL 32PLCC
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