Table 6: DC Operating Conditions (Continued)
Symbol Parameter Min Typ Max Unit Notes
ZQ External resistor value 115 120 125 Ω
Notes:
1. GDDR6 SGRAM devices are designed to tolerate PCB designs with separate V
DD
and
V
DDQ
power regulators.
2. DC bandwidth is limited to 20 MHz.
3. AC noise in the system is estimated at 50mV peak-to-peak for the purpose of DRAM de-
sign.
4. The reference voltage source and control for DQ and DBI_n pins are determined by half
V
REFD
, and V
REFD
level mode register bits.
5. Programmable V
REFD
levels are not supported with V
REFD2
.
6. The reference voltage source (external or internal) is determined at power‐up; the refer-
ence voltage level is determined by half V
REFC
and the V
REFC
offset mode register bit.
7. Programmable V
REFC
offsets are not supported with V
REFC2
.
8. V
IHR
and V
ILR
apply to boundary scan input pins TDI, TMS, and TCK. V
IHR
and V
ILR
apply
to EDC and CA inputs at reset when latching default device configurations. V
IHR
and V
ILR
also apply to CA, CABI_n, CKE_n, CK, DQ, DBI_n, EDC, and WCK inputs when boundary
scan mode is active and input data are latched in the capture-DR TAP controller state.
9. Use V
IHR
and V
ILR
when boundary scan mode is active and input data are latched in the
capture-DR TAP controller state.
10. This provides a minimum of 0.775V to a maximum of 0.975V with POD125, and is nor-
mally 70% of V
DDQ
. DRAM timings relative to CK cannot be guaranteed if these limits
are exceeded.
11. V
IDCK
is the magnitude of the difference between the input level in CK_t and the input
level on CK_c. The input reference level for signals other than CK_t and CK_c is V
REFC
.
12. V
IDWCK
is the magnitude of the difference between the input level on WCK_t and the
input level on WCK_c. The input reference level for signals other than WCK_t and
WCK_c is either V
REFC
, V
REFC2
, V
REFD
, or V
REFD2
.
13. The CK_t and CK_c input reference level (for timing referenced to CK_t and CK_c) is the
point at which CK_t and CK_c cross. Refer to the applicable timings in the AC Timings
table.
14. The WCK_t and WCK_c input reference level (for timing referenced to WCK_t and
WCK_c) is the point at which WCK_t and WCK_c cross. Refer to the applicable timings in
the AC Timings table.
Table 7: AC Operating Conditions (For Design Only
9
)
Symbol Parameter Min Typ Max Unit Notes
V
IHA(AC)
AC input logic HIGH voltage with V
REFC
for CA V
REFC
+ 0.165 − − V
V
ILA(AC)
AC input logic LOW voltage with V
REFC
for CA − − V
REFC
- 0.165 V
V
IHA2(AC)
AC input logic HIGH voltage with V
REFC2
for CA V
REFC
+ 0.333 − − V
V
ILA2(AC)
AC input logic LOW voltage with V
REFC2
for CA − − V
REFC
- 0.333 V
V
IHD(AC)
AC input logic HIGH voltage with V
REFD
for DQ,
DBI_n
V
REFD
+ 0.125 − − V
V
ILD(AC)
AC input logic LOW voltage with V
REFD
for DQ,
DBI_n
− − V
REFD
- 0.125 V
8Gb: 2 Channels x16/x8 GDDR6 SGRAM Networking
Operating Conditions
CCMTD-1412786195-10193
gddr6_sgram_8gb_brief_networking.pdf - Rev. G 8/18 EN
17
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