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CY2305SI-1H

P1-P3P4-P6P7-P9P10-P12P13-P15
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 7 of 15
t
8
Output Slew Rate
[6]
Measured between 0.8V and 2.0V using
Test Circuit #2
1––V/ns
t
J
Cycle to Cycle Jitter
[6]
Measured at 66.67 MHz, loaded outputs – 60 200 ps
t
LOCK
PLL Lock Time
[6]
Stable power supply, valid clock
presented on REF pin
––1.0ms
Switching Waveforms
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices
Parameter
[7]
Name Description Min Typ. Max Unit
t
1
t
2
1.4V 1.4V 1.4V
Figure 4. Duty Cycle Timing
OUTPUT
t
3
3.3V
0V
0.8V
2.0V 2.0V
0.8V
t
4
Figure 5. All Outputs Rise/Fall Time
1.4V
1.4V
t
5
OUTPUT
OUTPUT
Figure 6. Output-Output Skew
V
DD
/2
t
6
INPUT
OUTPUT
V
DD
/2
Figure 7. Input-Output Propagation Delay
V
DD
/2
V
DD
/2
t
7
CLKOUT, Device 1
CLKOUT, Device 2
Figure 8. Device-Device Skew
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CY2305
CY2309
Document #: 38-07140 Rev. *I Page 8 of 15
Typical Duty Cycle
[8]
and I
DD
Trends
[9]
for CY2305-1 and CY2309-1
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
Duty Cycle (%)
33 MHz
66 MHz
100 MHz
133 MHz
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Frequency (MHz)
Duty Cycle (%)
-40C
0C
25C
70C
85C
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
0123456789
# of Loaded Outputs
IDD (mA)
33 MHz
66 MHz
100 MHz
Notes
8. Duty Cycle is taken from typical chip measured at 1.4V.
9. I
DD
data is calculated from I
DD
= I
CORE
+ nCVf, where I
CORE
is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply Voltage (V);
f = frequency (Hz)).
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CY2305
CY2309
Document #: 38-07140 Rev. *I Page 9 of 15
Typical Duty Cycle
[8]
and IDD Trends
[9]
for CY2305-1H and CY2309-1H
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
Duty Cycle (%)
33 MHz
66 MHz
100 MHz
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
Duty Cycle (%)
33 MHz
66 MHz
100 MHz
133 MHz
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Frequency (MHz)
Duty Cycle (%)
-40C
0C
25C
70C
85C
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Frequency (MHz)
Duty Cycle (%)
-40C
0C
25C
70C
85C
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
160
0123456789
# of Loaded Outputs
IDD (mA)
33 MHz
66 MHz
100 MHz
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
160
0123456789
# of Loaded Outputs
IDD (mA)
33 MHz
66 MHz
100 MHz
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P1-P3P4-P6P7-P9P10-P12P13-P15

CY2305SI-1H

Mfr. #:
Buy CY2305SI-1H
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 3.3VZDB COM
Lifecycle:
New from this manufacturer.
Delivery:
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