ADM805LAN

ADM690A/ADM692A/ADM802L/M/ADM805L/M
–4–
REV. 0
Typical Performance Curves
I
OUT
– mA
V
OUT
– V
3
2.75
2
10 7020 30 40 50 60
2.5
2.25
R
OUT
= 9.3
Figure 1. Output Voltage vs. Load Current in Battery
Backup
10
0%
100
90
2µs
200mV
PFO
1.3V
PFI
1.2V
Figure 2. Power Fail Comparator Response Time L
H
10
0%
100
90
10µs
1V
5V
V
CC
RESET
4V
T
A
= +258C
Figure 3. ADM690A
RESET
Response Time
I
OUT
– mA
V
OUT
– V
5.00
4.92
4.84
20 20050 100 150
4.9
4.88
4.86
4.98
4.96
4.88
R
OUT
= 0.53
Figure 4. Output Voltage vs. Load Current in Normal
Operation
10
0%
100
90
2µs
200mV
T
A
= +258C
5V
PFO
1.3V
PFI
0V
1.2V
Figure 5. Power Fail Comparator Response Time H
L
10
0%
100
90
400ms1V
Figure 6.
RESET
Output Voltage vs. V
CC
ADM690A/ADM692A/ADM802L/M/ADM805L/M
–5–
REV. 0
BATTERY
SWITCHOVER
RESET
GENERATOR
WATCHDOG
TRANSITION DETECTOR
(1.6s)
4.65V*
1.25V
*4.4V FOR ADM692A/ADM802M/ADM805M
ADM690A
ADM692A
ADM802L
ADM802M
ADM805L
ADM805M
POWER FAIL
OUTPUT (PFO)
RESET
V
OUT
V
BATT
V
CC
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
(RESET)
( ) = ADM805L/M ONLY
Figure 7. Functional Block Diagram
POWER FAIL RESET, RESET
RESET is an active low output which provides a RESET signal
to the microprocessor whenever V
CC
is at an invalid level. When
V
CC
falls below the reset threshold, the RESET output is forced
low. The nominal reset voltage threshold is 4.65 V (ADM690A/
ADM802L/ADM805L or 4.4 V ADM692A/ADM802M/
ADM805M.
On power-up
RESET will remain low for 200 ms after V
CC
rises
above the reset threshold. This allows time for the power supply
and microprocessor to stabilize. On power-down, the
RESET
output remains low with V
CC
as low as 1 V. This ensures that
the microprocessor is held in a stable shutdown condition.
The guaranteed minimum and maximum thresholds are as follows:
ADM690A/ADM802L/ADM805L: 4.5 V and 4.75 V
ADM692A: 4.25 V and 4.5 V.
ADM802L: 4.55 V and 4.7 V
ADM802M: 4.3 V and 4.45 V
The ADM805L and ADM805M contain an active high reset
output. This is the complement of
RESET and is intended for
processors requiring an active high RESET signal.
The guaranteed minimum and maximum thresholds for the
ADM805 are:
ADM805L: 4.5 V and 4.75 V
ADM805M: 4.25 V and 4.5 V.
Watchdog Timer RESET, RESET
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
1.6 seconds, a RESET pulse is generated. The watchdog
timeout period restarts with each transition on the WDI pin. To
ensure that the watchdog timer does not time out, either a
high-to-low or low-to-high transition on the WDI pin must
occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each timeout period (1.6 s). The watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
connecting it to midsupply.
+5V
0V
+5V
0V
+5V
0V
+5V
0V
0V
3.0V
3.0V
t
RS
V
CC
V
OUT
RESET
RESET
PFO
V
BATT
= PFI = 3.0V
Figure 8. Timing Diagram
BATTERY SWITCHOVER SECTION
During normal operation with V
CC
higher than the reset
threshold, V
CC
is internally switched to V
OUT
via an internal
PMOS transistor switch. This switch has a typical on-resistance
of less than 1 and can supply up to 100 mA at the V
OUT
terminal. Once V
CC
falls below the reset threshold, the higher of
V
CC
or V
BATT
is switched to V
OUT
. This means that V
BATT
connects to V
OUT
only when V
CC
is below the reset threshold
and V
BATT
is greater than V
CC
.
V
OUT
is normally used to drive a RAM memory bank which
may require instantaneous currents of greater than 100 mA. If
this is the case, then a bypass capacitor should be connected to
V
OUT
. The capacitor will provide the peak current transients to the
RAM. A capacitance value of 0.1 µF or greater may be used.
A 9 MOSFET switch connects the V
BATT
input to V
OUT
during battery backup. This MOSFET has very low input-to-
output differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. The supply current in battery backup is
typically 0.05 µA.
Typically 3 V batteries are used as the backup supply. High
value capacitors, either standard electrolytic or the farad size
double layer capacitors, can also be used for short-term memory
back up. A small charging current of typically 10 nA (0.1 µA
max) flows out of the V
BATT
terminal. This current is useful for
maintaining rechargeable batteries in a fully charged condition.
This extends the life of the back up battery by compensating for
its self discharge current. Also note that this current poses no
problem when lithium batteries are used for back up since the
maximum charging current (0.1 µA) is safe for even the smallest
lithium cells.
If the battery-switchover section is not used, V
BATT
should be
connected to GND and V
OUT
should be connected to V
CC
.
ADM690A/ADM692A/ADM802L/M/ADM805L/M
–6–
REV. 0
Table I. Input and Output Status in Battery Backup Mode
Signal Status
V
OUT
V
OUT
is connected to V
BATT
via an internal
PMOS switch.
RESET Logic low.
RESET Logic high (ADM805L, ADM805M). The open
circuit output voltage is equal to V
OUT
.
PFI The power fail comparator is disabled
PFO Logic low.
WDI The watchdog timer is disabled
Power Fail Comparator
The power fail comparator is an independent comparator
that may be used to monitor the input power supply. The
comparator’s inverting input is internally connected to a 1.25
V reference voltage. The noninverting input is available at the
PFI input. This input may be used to monitor the input power
supply via a resistive divider network. When the voltage on the
PFI input drops below 1.25 V, the comparator output (
PFO)
goes low indicating a power failure. For early warning of power
failure the comparator may be used to monitor the preregulator
input simply by choosing an appropriate resistive divider
network. The
PFO output can be used to interrupt the
processor so that a shutdown procedure is implemented before
the power is lost.
1.25V
POWER FAIL
OUTPUT
(PFO)
POWER
FAIL
INPUT
INPUT
POWER
R1
R2
Figure 9. Power Fail Comparator
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is non-
inverting, hysteresis can be added simply by connecting a
resistor between the
PFO output and the PFI input as shown in
Figure 10. When
PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When
PFO is high, resistor
R3 sources current into the PFI summing junction. This results
in differing trip levels for the comparator. Further noise
immunity may be achieved by connecting a capacitor between
PFI and GND.
1.25V
(PFO)
INPUT
POWER
R1
R2
PFI
R3
TO
µP NMI
5V
PFO
0V
0V V
L
V
H
V
IN
V
H
=
1.25
1
+ R
1
R
2
+R
3
R
2
×
R
3
V
L
= 1
.25
+R
1
1.25
V
CC
1.25
R
2
R
3
V
MID
=
1.25
R
1
+R
2
R
2
Figure 10. Adding Hysteresis to the Power Fail
Comparator
TYPICAL APPLICATIONS
Figure 11 shows a typical power monitoring, battery backup
application. V
OUT
powers the CMOS RAM. Under normal
operating conditions with V
CC
present, V
OUT
is internally
connected to V
CC
. If a power failure occurs, V
CC
will decay and
V
OUT
will be switched to V
BATT
thereby maintaining power for
the CMOS RAM. A
RESET pulse is also generated when V
CC
falls below the reset threshold.
CMOS RAM
POWER
µP RESET
µP NMI
I/O LINE
µP SYSTEM
V
CC
µP POWER
V
OUT
RESET
PFO
WDI
GND
V
BATT
PFI
UNREGULATED
DC
R1
R2
+5V
BATTERY
+
Figure 11. Typical Application Circuit
The watchdog timer input (WDI) monitors an I/O line from the
µP system. This line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line
indicates that the µP system is not correctly executing its
program and may be tied up in an endless loop. If this happens,
a reset pulse is generated to initialize the processor.

ADM805LAN

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Supervisory Circuits 5V CMOS UP I.C.
Lifecycle:
New from this manufacturer.
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