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5V49EE903NLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
IDT5V49EE903
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 28
IDT5V49EE903 REV RR 071015
Package Outline and Package Dimensions (28-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
INDEX
AREA
1 2
28
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa C
c
L
Millimeters Inches
Symbol Min Max Min Max
A--1.20--0.047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.032 0.041
b 0.19 0.30 0.007 0.012
C 0.09 0.20 0.0035 0.008
D 9.60 9.80 0.378 0.386
E 6.40 BASIC 0.252 BASIC
E1 4.30 4.50 0.169 0.177
e 0.65 Basic 0.0256 Basic
L 0.45 0.75 0.018 0.030
0 8 0 8
aaa -- 0.10 -- 0.004
IDT5V49EE903
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 29
IDT5V49EE903 REV RR 071015
Package Outline and Package Dimensions (32-pin VFQFPN, 0.50mm pitch)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Part / Order Number Marking Shipping Packaging Package Temperature
5V49EE903PGGI See page 26 Tubes 28-pin TSSOP -40 to +85 C
5V49EE903PGGI8 See page 26 Tape and Reel 28-pin TSSOP -40 to +85 C
5V49EE903NLGI See page 26 Tray 32-pin VFQFPN -40 to +85 C
5V49EE903NLGI8 See page 26 Tape and Reel 32-pin VFQFPN -40 to +85 C
Thermal Base EP – exposed
thermal pad should be
externally connected to GND
IDT5V49EE903
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 30
IDT5V49EE903 REV RR 071015
Revision History
Rev. Date Originator Description of Change
A 4/22/09 R.Willner Advance Information.
B 5/04/09 R.Willner Identified VDDX (crystal oscillator power) and AVDD (analog power) on device.
C 6/04/09 R.Willner Add default configurations, pull-down resistor values on input pins.
Released Datasheet from Advanced Information.
D 06/10/09 R.Willner Updates: crystal load specs; “Output Duty Cycle” specs; addresses 0x07, 0x02 and 0xBF
in “Programming Registers” table.
E 08/26/09 R.Willner Updated 32-pin VFQFPN thermal data
F 10/05/09 R.Willner Changed IP3[3:0] to IP3[4:0] ; updated “Programming Registers Table”.
G 12/09/09 R.Willner Increased Max VCO frequency to 1300 MHz
H 02/23/10 R.Willner Updated Recommended Operation Conditions to include Vddx and AVdd parameters.
J 04/22/11 R.Willner Added 32QFN Landing Pattern diagram.
K 07/07/11 A. Tsui Updated package dimension drawing
L 12/6/11 R. Willner Correct pin description.
M 04/17/12 R. Willner 1. Change description for SDAT and SCLK pins.
2. Add new footnotes to pin descriptions table
3. Added section "Crystal Clock Selection"
4. Added logic diagram and Truth table for "SD/OE Pin Function" section.
5. Corrected register readback values for 0x52~0x54 and 0x7C~0x7F.
6. Update to QFN package drawing - exposed thermal pad callout.
N 06/04/12 A. Tsui 1. Updated SD-OE pin description; from (Default is active HIGH) to (Default is active
LOW)
2. Updated “OUTn” column in Truth Table with “High-Z” specs and added footnote 2,
“High-Z regardless of OEM bits”.
3. Updated “SD-OE Pin Function” section to reflect that SP is “0”changed from active
HIGH to active LOW, and SP is “1” changed from active LOW to active HIGH.
P 06/18/12 R.Willner Added Min/Max spread values to "Spread Spectrum Generation Specifications" table;
fMOD - Max. 120kHz; Down Spread - Min. -0.5%, Max. -4.0%; Center Spread - Min.
±0.25%, Max. ±2.0%
Q 09/24/12 R.Willner Slew Rate (t4) Output Load test conditions were changed from 15pF to 5pF.
R 07/10/15 A.B. Added the following note under AC Timing Electrical Characteristics table:
“Not guaranteed until customer specific configuration is approved by IDT.”
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

5V49EE903NLGI

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IDT
Description:
Clock Generators & Support Products EEPROM PROGRAMMABLE PLL
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New from this manufacturer.
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