UG-937 EVAL-1CH2CHSOICEBZ User Guide
Rev. 0 | Page 4 of 8
INPUT POWER
Each side of an iCoupler standard data isolator requires its own off-
board power source. On the silkscreen, the J1 and J2 screw
terminals are marked 1 for VDDx and 2 for GNDx.
Divided power and ground planes are present on Layer 2 and
Layer 3 of the PCB on each side of the isolation barrier. This
configuration is shown in Figure 9 and Figure 10, respectively.
DATA INPUT/OUTPUT (I/O) STRUCTURES
Each data channel has a variety of structures to help configure,
load, and monitor both the input and output. Figure 6 shows an
example of the routing from an external connection to the pin
of the device under test (DUT). Each data channel has similar
connections.
Starting at the external connection, the signal path is constructed in
the following order (see Figure 6 for the locations of these
components):
1. A pad layout for a PCB board edge mounted SMA
connector.
2. Two 0805 pads are provided where 100 resistors to
ground can be installed. The combined resistance is 50
to provide a termination for a standard coaxial cable.
3. A standard 0805 pad layout that allows the coaxial and
termination structures to be connected to the rest of the
signal path.
4. A 0603 pad layout between the signal path and VDDx for a
pull-up resistor, if required.
5. A populated 2-pin header to provide a signal ground pair
for use with clip leads or for temporarily shorting a channel
to ground.
6. Groupings of three open through holes, consisting of a
signal and two ground connections. These holes can be
used for hardwiring signal wires into the PCB, installing a
header to accept an active probe, or installing a 2-pin header
to allow adjacent channels to temporarily be shorted together.
7. A 0805 pad layout between the signal and GNDx where a
load capacitor or pull-down resistor can be installed.
Figure 5 shows many of the optional components installed, as well
as how the jumpers can be used to temporarily connect
channels. Figure 5 also shows a signal connected to the first
channel SMA, which is then fanned out to the top three
channels and monitored by an active scope probe.
BYPASS CAPACITANCE ON THE PCB
Several positions and structures are provided to allow optimal
bypass capacitance for the DUT on the evaluation board.
Provisions are made for optional surface-mount bulk capacitors
to be installed near the power connectors to compensate for
long cables to the power supply. Bypass capacitors are installed
near the iCoupler data isolator and consist of a 0.1 µF capacitor
for each DUT V
DDx
pin on the top side of the board.
The PCB also implements a distributed capacitive bypass. This
bypass consists of power and ground planes closely spaced on
the inner layers of the PCB, which reduces noise and the
transmission of EMI without using complex design features.
HIGH VOLTAGE CAPABILITY
This PCB is designed in adherence with 2500 V basic insulation
practices. High voltage testing beyond 2500 V is not recommended.
Do not rely on the evaluation board for safety functions.
Figure 6. Configuration and Monitoring Structures
NOTES
1. THE NUMBERED COMPONENTS IN THIS FIGURE CORRESPOND TO THE
DESCRIPTIONS IN THE DATA INPUT/OUTPUT STRUCTURES SECTION.
7 PULL DOWN
OR LOAD
4 PULL UP
3 CONNECT TO SMA
2 TERMINATION
1 SMA CONNECTOR PADS
5 2-PIN-HEADER
GND/SIGNAL
6 OPEN THROUGH HOLES
FOR ACTIVE PROBE HEADER
14279-006
