MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
6
Maxim Integrated
_______________Detailed Description
Converter Operation
The MAX1242/MAX1243 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 10-bit out-
put. Figure 3 shows the MAX1242/MAX1243 in their
simplest configuration. The MAX1242/MAX1243 convert
input signals in the 0V to V
REF
range in 9µs, including
T/H acquisition time. The MAX1242’s internal reference
is trimmed to 2.5V, while the MAX1243 requires an
external reference. Both devices accept external refer-
ence voltages from 1.0V to V
DD
. The serial interface
requires only three digital lines (SCLK,
CS,
and DOUT)
and provides an easy interface to microprocessors
(μPs).
The MAX1242/MAX1243 have two modes: normal and
shutdown. Pulling
SHDN
low shuts the device down and
reduces supply current below 10µA (V
DD
≤ 3.6V), while
pulling
SHDN
high or leaving it open puts the devices
into operational mode. A conversion is initiated by
pulling CS low. The conversion result is available at
DOUT in unipolar serial format. The serial-data stream
consists of a high bit, signaling the end of conversion
(EOC), followed by the data bits (MSB first).
Analog Input
Figure 4 illustrates the sampling architecture of the ana-
log-to-digital converter’s (ADC’s) comparator. The full-
scale input voltage is set by the voltage at REF.
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges
capacitor C
HOLD
. Bringing
CS
low ends the acquisition
interval. At this instant, the T/H switches the input side
of C
HOLD
to GND. The retained charge on C
HOLD
repre-
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0V within the limits of 10-
bit resolution. This action is equivalent to transferring a
charge from C
HOLD
to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
side of C
HOLD
switches back to AIN, and C
HOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
t
ACQ
, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. Acquisition time is calculated by:
t
ACQ
= 7(R
S
+ R
IN
) x 16pF
______________________________________________________________Pin Description
6 DOUT
Serial-Data Output. Data changes state at SCLK’s falling edge. High impedance when CS is high.
8 SCLK
3
SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1242/MAX1243 down to 15µA (max)
supply current. Both MAX1242 and MAX1243 are fully operational with either SHDN high or open. For
the MAX1242, pulling SHDN high enables the internal reference, and letting SHDN open disables the
internal reference and allows for the use of an external reference.
4 REF
Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1242;
bypass with a 4.7µF capacitor. External reference voltage input for MAX1243, or for MAX1242 with the
internal reference disabled. Bypass REF with a minimum of 0.1µF when using an external reference.
7
CS
Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is high
impedance.
5 GND Analog and Digital Ground
2 AIN Sampling Analog Input, 0V to V
REF
range
NAME FUNCTION
1 V
DD
Positive Supply Voltage: +2.7V to +5.25V
PIN
Serial-Clock Input. SCLK clocks data out at rates up to 2.1MHz.
