Full-Bridge PWM Motor Driver
A3953
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
value of t
OFF
and the minimum on-time pulse t
ON(min)
max that
occurs each time the PWM latch is reset. If the motor is not
rotating (as in the case of a stepper motor in hold/detent mode, a
brush dc motor when stalled, or at startup), the worst case value
of current regulation can be approximated by:
where t
OFF
= R
T
x C
T
, R
LOAD
is the series resistance of the load,
V
BB
is the motor supply voltage and t
ON(min)
max is specified in
the Electrical Characteristics table. When the motor is rotating,
the back EMF generated will influence the above relationship.
For brush dc motor applications, the current regulation is
improved. For stepper motor applications, when the motor is
rotating, the effect is more complex. A discussion of this subject
is included in the section on stepper motors below.
The following procedure can be used to evaluate the worst-case
slow current-decay internal PWM load current regulation in the
system:
1. Set V
REF
to 0 volts. With the load connected and the PWM
current control operating in slow current-decay mode, use an
oscilloscope to measure the time the output is low (sink on) for
the output that is chopping. This is the typical minimum on time
(t
ON(min)
typ) for the device.
2. The C
T
then should be increased until the measured value
of t
ON(min)
is equal to t
ON(min)
max as specified in the electrical
characteristics table.
3. When the new value of C
T
has been set, the value of R
T
should
be decreased so the value for t
OFF
= R
T
x C
T
(with the artificially
increased value of C
T
) is equal to the nominal design value.
4. The worst-case load-current regulation then can be measured
in the system under operating conditions.
PWM of the PHASE and ENABLE Inputs. The
PHASE and ENABLE inputs can be pulse-width modulated
to regulate load current. Typical propagation delays from the
PHASE and ENABLE inputs to transitions of the power outputs
are specified in the electrical characteristics table. If the internal
PWM current control is used, the comparator blanking function
is active during phase and enable transitions. This eliminates
false tripping of the over-current comparator caused by
switching transients (see RC Blanking section, above).
Enable PWM. With the MODE input low, toggling the
ENABLE input turns on and off the selected source and sink
drivers. The corresponding pair of flyback and ground-clamp
diodes conduct after the drivers are disabled, resulting in fast
current decay. When the device is enabled the internal current-
control circuitry will be active and can be used to limit the load
current in a slow current-decay mode.
For applications that PWM the ENABLE input and desire the
internal current-limiting circuit to function in the fast decay
mode, the ENABLE input signal should be inverted and
connected to the MODE input. This prevents the device from
being switched into sleep mode when the ENABLE input is low.
Phase PWM. Toggling the PHASE terminal selects which
sink/source pair is enabled, producing a load current that varies
with the duty cycle and remains continuous at all times. This
can have added benefits in bidirectional brush dc servo motor
applications as the transfer function between the duty cycle on
the PHASE input and the average voltage applied to the motor is
more linear than in the case of ENABLE PWM control (which
produces a discontinuous current at low current levels). For more
information see DC Motor Applications section, below.
Synchronous Fixed-Frequency PWM. The internal
PWM current-control circuitry of multiple A3953 devices can
be synchronized by using the simple circuit shown in figure 3.
A 555 IC can be used to generate the reset pulse/blanking signal
(t
1
) for the device and the period of the PWM cycle (t
2
). The
value of t
1
should be a minimum of 1.5 ms. When used in this
configuration, the R
T
and C
T
components should be omitted.
The PHASE and ENABLE inputs should not be PWM with this
circuit configuration due to the absence of a blanking function
synchronous with their transitions.
Figure 3
Synchronous Fixed-Frequency Control Circuit
Miscellaneous Information. A logic high applied to both
the ENABLE and MODE terminals puts the device into a sleep
mode to minimize current consumption when not in use.
An internally generated dead time prevents crossover currents
that can occur when switching phase or braking.
[(V
BB
– V
SAT(source+sink)
) x t
ON(min)
max] – (1.05(V
SAT(sink)
+ V
F
) x t
OFF
)
1.05 x (t
ON(min)
max + t
OFF
) x R
LOAD
I
AVE
≈
Dwg. EP-060
100 kΩ
20 kΩ
1N4001
2N2222
V
CC
RC
1
RC
N
t
1
2
t
