MP86963 –20A, 27V INTELLI-PHASE
TM
SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
MP86963 Rev.1.22 www.MonolithicPower.com 4
12/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
t
PDUH
t
PDLL
0V
SW
PWM
V
OUT
t
PDUL
t
PDLH
t
TSSHD
Figure 1—Timing Diagram
PIN FUNCTIONS
Pin # Name Description
1 NC Not Connected.
2 V
CC
Low-Side Driver Bias Supply. Decouple with a 1µF ceramic capacitor.
3 AGND Signal Ground.
4 EN
Active High On/Off Control. Pulling this Pin Low forces the SW Pin to be in a high
impedance state.
5 SYNC
Leaving this pin Open enables theLower Synchronous Switch. Pulling it Low forces
the Lower Switch into Diode Emulation mode.
6 PWM
Pulse Width Modulation Control. Accepts three-state input. Force PWM to midstate or
open to place SW into high impedance state.
7 V
CC
IO Reference voltage that connects to PWM driver supply.
8 BST
Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply
voltage. It is connected between SW and BST pins to form a floating supply across
the power switch driver.
9
Exposed Pad
IN
Supply Voltage. C
IN
is needed to prevent large voltage spikes from appearing at the
input.
10–18
Exposed Pad
GND Power Ground.
Exposed Pad SW Switch Output. These pins are fused together.