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FAN1655 Rev. 1.1.5
FAN1655 3A DDR Bus Termination Regulator
Applications Information
Output Capacitor selection
The JEDEC specification for DDR termination requires
that VTT stay within ±40mV of VREF, which must track
VDDQ/2 within 1%. During the initial load transient, the
output capacitor keeps the output within spec. To stay
within the 40mV window, the “load step” due to the load
transient current dropping across the output capacitor’s
ESR should be kept to around 25mV: where ESR <
is given in m
Ω
, and
∆
I is the maximum load current.
For example, to handle a 3A maximum load transient,
the ESR should be no greater than 8m
Ω
. Furthermore,
the output capacitor must be able to hold the load in
spec while the regulator recovers (about 15µS). A mini-
mum value of 470µF is recommended.
The FAN1655 requires a minimum of 100µF of input
capacitance with a maximum ESR value of 100m
Ω
to
insure stability.
Power Dissipation and Derating
The maximum output current (sink or source) for a 1.25V
output is:
where P
D(MAX)
is the maximum power dissipation which
is:
where T
J(MAX)
is the maximum die temperature of the IC
and T
A
is the operating ambient temperature.
FAN1655 has an internal thermal limit at 150°C, which
defines T
J(MAX)
. For the SOIC-14 package,
θ
JA
is given
at 88°C/W. Using equation 2, the maximum dissipation
at T
A
= 25°C is 1.4W, which is its rated maximum dissi-
pation.
The e-TSSOP or MLP package, however, use the PCB
copper to cool the IC through the thermal pad on the
package bottom. For maximum dissipation, this pad
should be soldered to the PCB copper, with as much
copper area as possible surrounding it to cool the pack-
age. Thermal vias should be placed as close to the ther-
mal pad as possible to transfer heat to other layers of
copper on the PCB. With large areas of PCB copper for
heat sinking, a
θ
JA
of under 40°C/W can easily be
achieved.
25
∆I
------
I
OUT MAX()
P
D MAX()
1.25
----------------------
=
P
D MAX()
T
J MAX()
T
A
–
θ
JA
----------------------------------
=
