MAX13036ATI+ Datasheet MAX13036ATI+, MAX13036ATI+T | P10-P12

MAX13036

The first four inputs (IN0–IN3) are intended for ground-

connected switches. The remaining four inputs (IN4–IN7)

can be programmed in sets of two for either ground-con-

nected or battery-connected switches by writing to the

M0 and M1 bits (see Table 5). The default state after

power-up is IN2–IN7 configured for ground-connected

switches, and IN0/IN1 configured for direct inputs.

All switch inputs have internal 16kΩ sense resistors to

detect switch transitions. Inputs configured for ground-

connected switches are pulled up to BAT and inputs

configured for battery-connected switches are pulled

down to GND. Figure 3 shows the switch input structure

for IN0 and IN1. IN0 and IN1 can be programmed as

direct inputs with level-shifted outputs (DO0 and DO1)

by clearing the WEND bit in the command register (nor-

mal mode only). When programmed as direct inputs,

IN0 and IN1 can be used for PWM or other signaling.

Clearing the WEND bit disables the sense resistors and

wetting currents on IN0 and IN1. When programmed as

direct inputs, the status of IN0 and IN1 is not reflected

in the status register, and interrupts are not allowed on

these inputs.

Switch Threshold Levels and

Hysteresis (BATREF, HYST)

Input thresholds for the remote switches are 50% of the

voltage applied to BATREF. The BATREF input is typi-

cally connected to the battery voltage before the

reverse-battery protection diode. The MAX13036 fea-

tures adjustable hysteresis on the switch inputs by con-

necting an external 0 to 900kΩ resistor from HYST to

ground (normal mode only). Short HYST to ground to

obtain the maximum hysteresis of (0.5 x V

BATREF

). The

approximate formula for hysteresis is given below:

To reduce power consumption, the adjustable hystere-

sis can be disabled by setting [SC2:SC1:SC0 = 1:1:0]

in the command register. When the adjustable hystere-

sis is disabled, the hysteresis is set to 0.166 x V

BATREF.

Switch Debounce and Deglitch

The switch inputs IN0–IN7 share a common program-

mable debounce timer to increase the noise immunity

of the system in normal and scan mode. The switch

debounce time is set by connecting a capacitor

between the t

DEB

input and ground. The minimum

value of this capacitor is 500pF and the maximum value

is 10nF, corresponding to a debounce time of 5ms to

100ms respectively. To calculate other debounce times

the following formula should be used:

C(nF) = t

DEB

(ms)/10

All switch input glitches of less than 20µs in duration

are automatically rejected by the MAX13036.

Debounce in Normal Mode

When a change of state occurs at the switch input the

debounce timer starts. If the new state is stable for at

least t

DEB

, the status register is updated and an inter-

rupt is generated (if enabled). If the input returns to its

previous state before the debounce time has elapsed,

an interrupt is not generated and the status register is

not updated.

Debounce in Scan Mode

A change of state at the switch input causes the device

to automatically enter normal mode and the debounce

timing to start. The device remains in normal mode as

long as the input state differs from the previous state.

As soon as the debounce time ends, the status register

is updated, an interrupt is generated, and the device

re-enters scan mode.

If the input returns to its previous state before the end

of the debounce time, the device re-enters scan mode,

an interrupt is not generated, and the status register is

not updated.

HYST

HYST(k )

BATREF

⎡

⎣

⎢

⎤

⎦

⎥

0 166

123

(( )

()

Automotive Contact Monitor

and Level Shifter

10 ______________________________________________________________________________________

MAX13036

16kΩ*

NOTES:

* WETTING CURRENT AND PULLUP/DOWN RESISTORS ARE

CONTROLLED BY THE WEN AND WEND BITS IN THE COMMAND

WETTING*

CURRENT

IN0, IN1

BAT

CONTROL

LOGIC

Figure 3. Input Structure of IN0 and IN1

Wetting Current (WET)

The MAX13036 features adjustable wetting current to

any closed switch to clean switch contacts that are

exposed to adverse conditions. The wetting current is

set by connecting a 30kΩ to 330kΩ resistor from WET

to ground. A 30kΩ resistor corresponds to a wetting

current of 40mA (typ) and a 330kΩ resistor corre-

sponds to a 7.5mA (typ) wetting current. See the

Typical Operating Characteristics

section for the rela-

tionship between the wetting current and R

WET

The WEN and WEND bits in the command register

enable and disable the wetting currents and the WTOFF

bit allows the wetting current to be activated for a dura-

tion of 20ms (typ) (see the

Command Register

section).

Disabling wetting currents, or limiting the active wetting

current time reduces power consumption. The default

state upon power-up is all wetting currents disabled.

Wetting current is activated on closed switches just

after the debounce time. The wetting current pulse

starts after the debounce time. A wetting current pulse

is provided to all closed switches when a valid input

change is detected. Wetting current rise and fall times

are controlled to enhance EMC performance. There is

one wetting current timer for all switch inputs.

Therefore, it is possible to observe wetting pulses

longer than expected whenever two switches turn on in

sequence and are spaced out less than t

WET

. In scan

mode, the wetting current is enabled during the polling

pulse only.

When using wetting currents, special care must be taken

to avoid exceeding the maximum power dissipation of the

MAX13036 (see the

Applications Information

section).

Switch Outputs (DO0, DO1)

DO0 and DO1 are direct level-shifted outputs of the

switch inputs IN0 and IN1 when the WEND bit of the

command register is cleared and when operating in

normal mode. When configured as direct inputs, the

wetting currents and sensing resistors are disabled on

IN0 and IN1. DO0 and DO1 are tri-stated when the

WEND bit is set or when operating in scan mode.

When programmed as direct inputs, the status of IN0

and IN1 are not reflected in the status register and

interrupts are not allowed on these inputs.

Interrupt Output (

INT

)

INT is an active-low, open-drain output that asserts

when any of the switch inputs changes state, as long

as the particular input is enabled for interrupts (set by

clearing P7–P0 in the command register). A pullup

resistor to V

is needed on INT. INT is cleared when CS

is driven low for a read/write operation.

The INT output will still assert when V

is absent provid-

ed that it is pulled up to a different supply voltage.

Thermal Protection (

)

The MAX13036 features thermal protection that pre-

vents the device from being damaged by overheating.

When the internal temperature of the device exceeds

the thermal warning threshold of +170°C (typ), all wet-

ting currents are disabled. The MAX13036 returns to

normal operation after the internal temperature

decreases below +155°C (typ). The thermal shutdown

does not activate below +150°C. The thermal protec-

tion feature is disabled when WEN = 0 or when all

inputs are open.

An open-drain, active-low output (OT) asserts low when

the internal temperature of the device rises above the

thermal warning threshold. OT is immediately cleared

when the CS input is driven low for write/read opera-

tions, regardless of whether the temperature is above

the threshold or not. The overtemperature status of the

MAX13036 can also be monitored by reading the OT bit

in the status register. The OT bit is set when the internal

temperature rises above the temperature threshold and

it is cleared when the temperature falls below the tem-

perature hysteresis level. This allows a microprocessor

(µP) to monitor the overtemperature status, even if the

OT output has been cleared. See Figure 4 for an exam-

ple timing diagram of the overtemperature alerts.

If desired, the OT and INT outputs can be connected to

the same µP GPIO in a wired-OR configuration to save a

µP pin. The OT output still asserts when V

is absent

provided that it is pulled up to a different supply voltage.

Serial Peripheral Interface

(

, SD0, SDI, CLK)

The MAX13036 operates as a Serial Peripheral Interface

(SPI) slave device. An SPI master accesses the

MAX13036 by reading from a status register and writing

to a command register. Both registers are 16 bits long

and are accessed most significant bit (MSB) first.

MAX13036

Automotive Contact Monitor

and Level Shifter

______________________________________________________________________________________ 11

TEMPERATURE

OT BIT

Figure 4. Example Timing Diagram of the Overtemperature Alerts

MAX13036

On the falling edge of CS, the status register is immedi-

ately loaded to an internal shift register and the contents

are transferred out of the SDO output on the rising edge

of CLK. Serial data on the SDI input is latched into the

shift register on the falling edge of CLK. On the rising

edge of CS, the contents of the shift register are copied

to the command register (see Figure 5). The status and

command registers are 16 bits wide, so it is essential to

clock a total of 16 bits while CS is low for the input and

output data to be valid. When CS is high, the SDO out-

put is high-impedance and any transitions on CLK and

SDI are ignored. The INT and OT flags are cleared on

the CS falling edge. Input status changes occurring

during the CS reading/writing operation are allowed. If

a switch status changes when CS is low, the interrupt is

asserted as usual. This allows the part to be used even

if V

is absent provided that the INT output is pulled up

to another supply voltage.

Status Register

The status register contains the status of the switches

connected to IN7 through IN0 and it also contains an

overtemperature warning bit (see Table 1). The status

Notes:

Bits 15–8: Switch 7 Through 0 Status (SW7–SW0)

SW7 through SW0 reflect the status of the switches

connected to inputs IN7 through IN0, respectively.

Open switches are returned as a [0] and closed switch-

es are returned as a [1].

Bit 7: Overtemperature Warning (OT)

The OT bit returns a [1] when the internal temperature

of the MAX13036 is above the temperature warning

threshold of +170°C (typ). The OT bit returns a [0]

when the MAX13036 is either below the temperature

threshold, or it has fallen below the temperature hys-

teresis level following an overtemperature event.

Bits 6–0: Unused

Bits 6 through 0 are unused and should be ignored.

Command Register

The command register is used to configure the

MAX13036 for various modes of operation and is

accessed by an SPI-compatible master (see Table 2).

The power-on reset (POR) value of the command regis-

ter is 0x00.

Automotive Contact Monitor

and Level Shifter

12 ______________________________________________________________________________________

Table 1. Status Register

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NAME SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 OT — — — — — — —

Table 2. Command Register

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NAME WTOFF SC2 SC1 SC0 WEN WEND M1 M0 P7 P6 P5 P4 P3 P2 P1 P0

POR 0 0000 0 0000000000

CLK

* = UNUSED.

SDI

SDO

STATUS REGISTER

IS COPIED TO

SHIFT REGISTER

SHIFT REGISTER IS

COPIED TO COMMAND

14131211109876543210

WTOFF

SC2 SC1 SC0 WEN WEND M1 M0 P7 P6 P5 P4 P3 P2 P1 P0

SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 OT * * * * * * *

Figure 5. SPI Read/Write Example

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MAX13036ATI+

Mfr. #:

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Description:

Interface - Specialized Auto Contact Monitor & Level Shifter

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MAX13036ATI+

MAX13036ATI+

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