Introduction to RVI and RVT
ARM DUI 0515B Copyright © 2010 ARM. All rights reserved. 2-7
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2.6 Debug extensions to the ARM processor
The debug extensions consist of several scan chains around the processor, and some additional
signals that are used to control the behavior of the processor for debug purposes. The most
significant of these additional signals are:
BREAKPT This processor signal enables external hardware to halt processor execution for
debug purposes. When HIGH during an instruction fetch, the instruction is tagged
as breakpointed, and the processor stops if this instruction reaches the execute
stage of the pipeline.
DBGRQ This processor signal is a level-sensitive input that causes the processor to enter
debug state when the current instruction has completed.
DBGACK This processor signal is an output from the processor that goes HIGH when the
processor is in debug state so that external devices can determine the current state
of the processor.
RVI uses these, and other signals, through the debug interface of the processor, for example by
writing to the control register of the EmbeddedICE logic. For more details, see the topic that
describes the debug interface support of the ARM datasheet or technical reference manual for
your processor (for example, the ARM7TDMI (Rev 4) Technical Reference Manual).
2.6.1 See also
Concepts
• EmbeddedICE debug architecture and debug monitor differences on page 2-8.
