8©2016June 28, 2016 Integrated Device Tech- June 28, 2016
87973I-147 Data Sheet
Table 5. Input Frequency Characteristics, V
DD
= V
DDA
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * feedback divide" is in the VCO range of 240MHz to 500MHz.
AC Electrical Characteristics
Table 6. AC Characteristics, V
DD
= V
DDA
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and
the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
F
IN
Input Frequency
CLK0, CLK1; NOTE 1 120 MHz
FRZ_CLK 20 MHz
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency
÷2 250 MHz
÷4 125 MHz
÷6 83.33 MHz
÷8 62.5 MHz
÷10 50 MHz
÷12 41.66 MHz
t(Ø)
Static Phase Offset;
NOTE 1
CLK0
QFB ÷ 8,
In Frequency = 50MHz
-10 145 300 ps
CLK1 -65 90 245 ps
CLK, nCLK -130 18 165 ps
tsk(o) Output Skew; NOTE 2, 3 200 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 3 All Banks ÷ 4 55 ps
f
VCO
PLL VCO Lock Range 240 500 MHz
t
LOCK
PLL Lock Time; NOTE 4 10 ms
t
R
/ t
F
Output Rise/Fall Time 0.8V to 2V 150 700 ps
odc Output Duty Cycle 45 55 %
t
PZL,
t
PZH
Output Enable Time; NOTE 4 10 ns
t
PLZL,
t
PHZ
Output Disable Time; NOTE 4 8ns
