74F373PC

© 2000 Fairchild Semiconductor Corporation DS009523 www.fairchildsemi.com
May 1988
Revised September 2000
74F373 Octal Transparent Latch with 3-STATE Outputs
74F373
Octal Transparent Latch with 3-STATE Outputs
General Description
The 74F373 consists of eight latches with 3-STATE outputs
for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE
) is LOW. When OE is HIGH the bus output is in
the high impedance state.
Features
Eight latches in a single package
3-STATE outputs for bus interfacing
Guaranteed 4000V minimum ESD protection
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F373MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F373
Unit Loading/Fan Out
Functional Description
The 74F373 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE
) input. When OE is LOW, the buffers are in the
bi-state mode. When OE
is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance State
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
D
0
D
7
Data Inputs 1.0/1.0 20 µA/0.6 mA
LE Latch Enable Input (Active HIGH) 1.0/1.0 20
µA/0.6 mA
OE
Output Enable Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
O
0
O
7
3-STATE Latch Outputs 150/40 (33.3) 3 mA/24 mA (20 mA)
Inputs Output
LE OE
D
n
O
n
HLH H
HLL L
LLXO
n
(no change)
XHX Z
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74F373
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature 65°C to +150°C
Ambient Temperature under Bias
55°C to +125°C
Junction Temperature under Bias
55°C to +150°C
V
CC
Pin Potential to Ground Pin 0.5V to +7.0V
Input Voltage (Note 2)
0.5V to +7.0V
Input Current (Note 2)
30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output
0.5V to V
CC
3-STATE Output 0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambient Temperature 0
°C to +70°C
Supply Voltage
+4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage 1.2 V Min I
IN
= 18 mA
V
OH
Output HIGH 10% V
CC
2.5
VMin
I
OH
= 1 mA
Voltage 10% V
CC
2.4 I
OH
= 3 mA
5% V
CC
2.7 I
OH
= 1 mA
5% V
CC
2.7 I
OH
= 3 mA
V
OL
Output LOW Voltage 10% V
CC
0.5 V Min I
OL
= 24 mA
I
IH
Input HIGH
5.0 µAMaxV
IN
= 2.7V
Current
I
BVI
Input HIGH Current
7.0 µAMaxV
IN
= 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
I
ID
= 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current 0.6 mA Max V
IN
= 0.5V
I
OZH
Output Leakage Current 50 µAMaxV
OUT
= 2.7V
I
OZL
Output Leakage Current 50 µAMaxV
OUT
= 0.5V
I
OS
Output Short-Circuit Current 60 150 mA Max V
OUT
= 0V
I
ZZ
Bus Drainage Test 500 µA0.0VV
OUT
= 5.25V
I
CCZ
Power Supply Current 38 55 mA Max V
O
= HIGH Z

74F373PC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Latches Octal Trans Latch
Lifecycle:
New from this manufacturer.
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