© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 2
1 Publication Order Number:
NCV8851−1/D
NCV8851-1
Automotive Grade
Synchronous Buck
Controller
The NCV8851−1 is an adjustable output, synchronous buck
controller, which drives dual N−channel MOSFETs, ideal for high
power applications. Average current mode control is employed for
very fast transient response and tight regulation over wide input
voltage and output load ranges. The IC incorporates an internal fixed
6.0 V low−dropout linear regulator (LDO), which supplies charge to
the switch mode power supply’s (SMPS) bottom gate driver, limiting
the power lost to excess gate drive. The IC is designed for operation
over a wide input voltage range (4.5 V to 40 V) and is capable of 10 to
1 voltage conversion at 500 kHz.
Additional controller features include undervoltage lockout,
internal soft−start, low quiescent current sleep mode, programmable
frequency, SYNC function, average current limiting, cycle−by−cycle
overcurrent protection and thermal shutdown.
Features
Average Current Mode Control
0.8 V ±2% Reference Voltage
Wide Input Voltage Range of 4.5 V to 40 V
Operates through Load Dump Conditions
6.0 V Low−dropout Linear Regulator (LDO)
Input UVLO (Undervoltage Lockout)
Internal Soft−start
1.0 mA Maximum Quiescent Current in Sleep Mode
Adaptive Non−overlap Circuitry
180 ns Minimum High−side Gate Off−time
Programmable Fixed Frequency – 170 kHz to 500 kHz
External Clock Synchronization up to 600 kHz
Average Current Limiting (ACL)
Cycle−by−Cycle Overcurrent Protection (OCP)
Thermal Shutdown (TSD)
This is a Pb−Free Device
Applications
Automotive Systems Requiring High Current
Pre−regulated Supply for Low−voltage SMPSs and LDOs
MARKING DIAGRAM
V8851−1 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
V88
51−1
ALYWG
G
Device Package Shipping
ORDERING INFORMATION
TSSOP−20
SUFFIX DB
CASE 948E
(Note: Microdot may be in either location)
NCV8851−1DBR2G TSSOP−20
(Pb−Free)
2500 / Tape &
Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
www.onsemi.com
NCV8851−1
www.onsemi.com
2
V
CLAMP
Figure 1. Functional Block Diagram
Figure 2. Application Schematic
V
IN
EN
V
IN_IC
SYNC
R
OSC
C
COMP
12
11
C
FB
CS
OUT
V
COMP
V
FB
20
1
3
15
16
17
14
13
9
6V
OUT
BST
GH
V
SW
4
5
6
7
8
2
19
18
10
GL
PGND
V
IN_CS
CSP
CSN
AGND
CSA
Fault
ACL
BST
6V
OUT
Fault
V
ACL
+
+
V
REF
V
SS
+
VEA
CEA
OCP
V
OCP
Nonoverlap
+
V
REF
PWM
TSD
Enable
UVLO
Fixed−Frequency
Oscillator
Ramp Clock
Max
Duty
Reset
Dominant
Fault
Logic
LDO
Enable
LDO
I
LIMIT
Soft Start
V
SS
Min
On
Time
Q
Q
S
R
12
11
3
1
20
R
OSC
R
OSC
SYNC
V
IN_IC
EN
V
IN
15
16
17
10
V
IN
C
C2
C
COMP
C
C1
R
C1
R
C2
CS
OUT
AGND
C
FB
14
13
18
19
2
8
7
6
5
4
9
L
C
+
+
V
OUT
R
S
R
V1
C
V1
C
V2
V
COMP
V
FB
CSN
CSP
R
F1
R
F0
PGND
V
IN_CS
GL
V
SW
GH
BST
6V
OUT
D
BST
V
IN
+
+
C
BST
Q1
Q2
Note: This part is recommended for synchronous use only.
NCV8851−1
www.onsemi.com
3
PACKAGE PIN DESCRIPTIONS − 20 Lead TSSOP
Package Pin# Pin Symbol Function
1 SYNC External clock synchronization input.
2 V
IN_CS
Supply input for the internal current sense amplifier.
3 V
IN_IC
Supply input for internal logic and analog circuitry.
4 BST Supply input for the floating top gate driver. An external diode, D
BST
, from 6V
OUT
and a
0.1 mF to 1 mF capacitor, C
BST
, to V
SW
forms a boost circuit.
5 GH Gate driver output for the external high−side NMOS FET.
6 V
SW
Switch−node. This pin connects to the source of the high−side MOSFET and drain of the
low−side MOSFET. This pin serves as the switch output to the inductor.
7 GL Gate driver output for the external low−side NMOS FET.
8 PGND Power Ground. Ground reference for the high−current path including the NMOS FETs and
output capacitor.
9 6V
OUT
Output of internal fixed 6.0 V LDO.
10 AGND Analog Ground. Ground reference for the internal logic and analog circuitry as well as R
OSC
and the compensators.
11 EN Enable input. When disabled, the LDO, internal logic and analog circuitry and gate drivers
enter sleep mode, drawing under 1 mA.
12 V
IN
Supply input for the SMPS.
13 V
FB
SMPS’s voltage feedback. Inverting input to the voltage error amplifier. Connect to V
OUT
through a resistive divider.
14 V
COMP
SMPS’s voltage error amplifier output and non−inverting input to the current error amplifier.
15 C
COMP
SMPS’s current error amplifier output and inverting input to the PWM comparator.
16 C
FB
SMPS’s current feedback. Inverting input to the current error amplifier.
17 CS
OUT
Single−ended output of the differential current sense amplifier. Connect to C
FB
through a
resistor. Non−inverting input to the cycle−by−cycle overcurrent comparator.
18 CSN Differential current sense amplifier inverting input.
19 CSP Differential current sense amplifier non−inverting input.
20 R
OSC
Oscillator’s frequency adjust pin. Resistor to ground sets the oscillator frequency.
MAXIMUM RATINGS (Voltages are with respect to AGND unless otherwise indicated.)
Rating
Value Unit
Dc Supply Voltage (V
IN
)
Peak Transient Voltage (Load Dump)
−0.3 to 40
45
V
Dc Supply Voltage (V
IN_CS
) 46 V
Dc Supply Voltage (V
IN_IC
) 6.5 V
Pin Voltage (V
SW
)
t
50 ns
−0.7 to 40.7
−2
V
Pin Voltage (BST, GH) 46 wrt PGND
7 wrt V
SW
V
Pin Voltage (GL) −0.3 to 7 wrt PGND V
Pin Voltage (EN) −0.3 to 40 V
Pin Voltage (CSP, CSN) −0.3 to 10 V
Pin Voltage (V
FB
, V
COMP
, CS
OUT
, C
FB
, C
COMP
, SYNC, R
OSC
, 6V
OUT
) −0.3 to 7 V
Pin Voltage (PGND) −0.3 to 0.3 V
Operating Junction Temperature −40 to 150 °C
Storage Temperature Range −65 to 150 °C
Peak Reflow Soldering Temperature: Lead−free 60 to 150 seconds at 217°C 265 peak °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

NCV8851-1DBR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LDO Voltage Controllers SYNC BUCK CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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