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ADC0801S040TS/C1,1
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
3ADC0801S040_3
© IDT 2012. All rights r
eserved.
Product data sheet
Rev
. 03 —
2 July 2012
10 of 18
Integrated Device T
echnology
ADC0801S040
Single 8 bit
s ADC, up to 40 MHz
sample N + 1
sample N
CLK
014aaa508
sample N + 2
sample N + 1
sample N
sample N + 2
50 %
VI
D
ATA
D0 to D7
V
DDO
0 V
50 %
D
ATA
N + 1
D
ATA
N
D
ATA
N
−
1
D
ATA
N
−
2
t
d(o)
t
w(clk)H
t
w(clk)L
t
d(s)
t
h(o)
Fig 4.
Timing di
agram
3ADC0801S040_3
© IDT 2012. All rights r
eserved.
Product data sheet
Rev
. 03 —
2 July 2012
1
1 of 18
Integrated Device T
echnology
ADC0801S040
Single 8 bit
s ADC, up to 40 MHz
LOW
HIGH
HIGH
LOW
ADC0801S040
V
DDD
V
DDD
S1
SLEEP
SLEEP
output
data
output
data
10 %
50 %
50 %
90 %
50 %
t
dLZ
t
dZL
t
dHZ
t
dZH
20 pF
3
.
3
k
Ω
S1
TEST
V
DDD
t
dLZ
V
DDD
t
dZL
GND
t
dZH
t
dHZ
GND
014aaa496
frequency on pin SLEEP = 100 kHz.
Fig 5.
Timi
ng diagram and tes
t condit
ions of 3-st
ate output delay time
014aaa501
−
0.047
0.065
−
0.160
0.178
0.291
A
(LSB)
−
0.272
codes
0
272
204
68
136
Fig 6.
T
ypical Integral Non-Linearity (I
NL) performance
3ADC0801S040_3
© IDT 2012. All rights r
eserved.
Product data sheet
Rev
. 03 —
2 July 2012
12 of 18
Integrated Device T
echnology
ADC0801S040
Single 8 bit
s ADC, up to 40 MHz
014aaa502
−
0.025
0.032
−
0.84
0.091
0.150
A
(LSB)
−
0.143
codes
0
272
204
68
136
Fig 7.
T
ypical Differential No
n-Linearity (DNL)
performance
014aaa497
code 255
code 0
50 %
50 %
CLK
VI
t
s(LH)
t
s(HL)
50 %
50 %
5
ns
5
ns
2
ns
2
ns
Fig 8.
An
alog inpu
t se
ttling-time diagram
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
ADC0801S040TS/C1,1
Mfr. #:
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Manufacturer:
Description:
IC ADC 8BIT SAR 20SSOP
Lifecycle:
New from this manufacturer.
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ADC0801S040TS/C1,1