MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
10 ______________________________________________________________________________________
Figure 6. Daisy-chained or individual MAX532s are simultaneously updated by bringing CS high when using the 3-wire interface
(LDAC = DGND).
SCLK
DIN
CS
TO OTHER 
SERIAL DEVICES
MAX532
SCLK
DIN
CS
DOUT
LDAC
+5V +5V +5V
R
P
R
P
1k
1k
MAX532
SCLK
DIN
CS
DOUT
LDAC
MAX532
SCLK
DIN
CS
DOUT
LDAC
SCLK
DIN
CS
MAX532
SCLK
DIN
CS
LDAC
R
P
1k
Figure 7. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3, . . .,
are driven separately, thus controlling which data are written to devices 1, 2, 3, . . . .
CS
LDAC
SCLK
DIN
CS
LDAC
SCLK
DIN
MAX532
CS
LDAC
SCLK
DIN
TO OTHER 
SERIAL DEVICES
MAX532
MAX532
DIN
SCLK
LDAC
CS1
CS2
CS3
With the values of t
RC
given in Table 1, t
CSS0
is always
given by t
DV
+ t
DS
. For different values of R or C, t
RC
must be calculated to determine t
CSS0
.
Additionally, the maximum clock frequency is limited to
1
f
CLK
(max) = ————————————— .
2 x (t
DO
+ t
RC
-15ns + t
DS
)
For example, with t
RC
= 15ns (5V ±10% supply with
1k pull-up), the maximum clock frequency is 2MHz.
Digital-to-Analog Section
Figure 8 shows a simplified circuit diagram for one of
the DACs and the output amplifier.
A segmented scheme is used to improve linearity,
whereby the two MSBs of the 12-bit data word are
decoded to drive the three switches, SA, SB, and SC.
The remaining ten bits drive the switches S0 through S9
in a standard R-2R ladder configuration.
Each of the switches, SA, SB, and SC, steers 1/4 of the
total reference current with the remaining 1/4 passing
through the R-2R section.
The output amplifier and feedback resistor perform the
current-to-voltage conversion, giving the following:
VOUT_ = -D x VREF_,
where _ denotes A or B, and D is the fractional representa-
tion of the digital word. (D can be set from 0 to 4095/4096.)
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
______________________________________________________________________________________ 11
V
PULL-UP
(V) C (pF) R
P
(k)t
RC
(ns)
4.5 20 1 15
4.5 35 1 27
4.5 50 1 38
4.5 100 1 76
4.5 150 1 114
11.4 20 3 14
11.4 35 3 25
11.4 50 3 35
11.4 100 3 71
11.4 150 3 106
13.5 20 3 12
13.5 35 3 21
13.5 50 3 29
13.5 100 3 59
13.5 150 3 88
Table 1. t
RC
Delay Times
RR R
2R 2R 2R 2R 2R 2R 2R
SC SB SA S9 S8 S0
R/2
RFB_
VOUT_
AGND_
SHOWN FOR ALL 1s ON DAC
VREF_
Figure 8. Simplified D/A Circuit Diagram
DACA
AGNDAV
SS
DGND
RFBA
VOUTA
V
OUT
V
IN
-12V to -15V
V
DD
VREFA
+12V to +15V
MAX532
Figure 9. Unipolar Binary Operation
MAX532
Output Amplifiers
The output amplifiers are stable with any combination
of resistive loads 2k and capacitive loads 100pF.
They are internally compensated, and settle to ±0.01%
FSR (1/2LSB) in 2.5µs.
Unipolar Configuration
Figure 9 shows DACA connected for unipolar binary
operation. Similar connections apply for DACB. When
V
IN
is an AC signal, the circuit performs two-quadrant
multiplication. Table 2 shows the codes for this circuit.
Bipolar Operation
Figure 10 shows the MAX532 connected for bipolar
operation. The coding is offset binary, as shown in
Table 3. When V
IN
is an AC signal, the circuit performs
four-quadrant multiplication. To maintain gain error
specifications, resistors R1, R2, and R3 should be ratio-
matched to 0.01%.
__________Applications Information
Layout, Grounding, and Bypassing
For best system performance, use printed circuit boards
with separate analog and digital ground planes. Wire-
wrap boards are not recommended. The two ground
planes should be tied together at the low-impedance
power-supply source, as shown in Figure 11.
The board layout should ensure that digital and analog
signal lines are kept separate from each other as much
as possible. Do not run analog and digital lines parallel
to one another.
The output amplifiers are sensitive to high-frequency
noise in the V
DD
and V
SS
power supplies. Bypass
these supplies to the analog ground plane with 0.1µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best noise rejection.
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
12 ______________________________________________________________________________________
1111 1111 1111
-V
IN
x (4095/4096)
1000 0000 0000
-V
IN
x (2048/4096) = -1/2V
IN
0000 0000 0001
-V
IN
x (1/4096)
0000 0000 0000 0V
DAC Latch Contents
Table 2. Unipolar Code Table
1LSB = V
IN
/4096
DAC_
AGND_
V
SS
DGND
RFB_
VOUT_
V
IN
-12V to -15V
V
DD
VREF_
+12V to +15V
MAX532
V
OUT
R1
20k
R2
20k
R3
10k
Figure 10. Bipolar Operation
V
DD
V
SS
AGNDA AGNDB DGND
MAX532
+15V -15V AGND +5V DGND
ANALOG
SUPPLY
DIGITAL
SUPPLY
DIGITAL
CIRCUITRY
+5V DGND
Figure 11. Power-Supply Grounding
Table 3. Bipolar Code Table
DAC Latch Contents
1111 1111 1111
+V
IN
x (2047/2048)
1000 0000 0001
+V
IN
x (1/2048)
1000 0000 0000 0V
0111 1111 1111
-V
IN
x (1/2048)
1LSB = V
IN
/2048
0000 0000 0000
-V
IN
+ (2048/2048) = -V
IN
MSB LSB
Analog Output, V
OUT
MSB LSB
Analog Output, V
OUT

MAX532ACPE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 12-Bit 2Ch Precision DAC
Lifecycle:
New from this manufacturer.
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