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© 2000 IXYS All rights reserved
IXYS reserves the right to change limits, test conditions, and dimensions.
N-Channel Enhancement Mode
Avalanche Rated
High dv/dt, Low t
rr
, HDMOS
TM
Family
Preliminary data sheet
Features
• Low profile, high power package
• Long creep and strike distances
• Easy up-grade path for TO-220
designs
• Low R
DS (on)
low Qg process
• Rugged polysilicon gate cell structure
• Unclamped Inductive Switching (UIS)
rated
• Low package inductance
- easy to drive and to protect
• Fast intrinsic Rectifier
Applications
• DC-DC converters
• Synchronous rectification
• Battery chargers
• Switched-mode and resonant-mode
power supplies
• DC choppers
• AC motor control
• Temperature and lighting controls
• Low voltage relays
Advantages
• High power, low profile package
• Space savings
• High power density
98579B (5/31/00)
G = Gate, D = Drain,
S = Source, TAB = Drain
(TAB)
G
D
S
é
Symbol Test Conditions Maximum Ratings
V
DSS
T
J
= 25°C to 150°C 500 V
V
DGR
T
J
= 25°C to 150°C; R
GS
= 1 MW 500 V
V
GS
Continuous ±20 V
V
GSM
Transient ±30 V
I
D25
T
C
= 25°C32A
I
DM
T
C
= 25°C, pulse width limited by T
JM
128 A
I
AR
T
C
= 25°C32A
E
As
T
C
= 25°C 1.5 J
E
AR
T
C
= 25°C45mJ
dv/dt I
S
£ I
DM
, di/dt £ 100 A/ms, V
DD
£ V
DSS
, 5 V/ns
T
J
£ 150°C, R
G
= 2 W
P
D
T
C
= 25°C 360 W
T
J
-55 ... +150 °C
T
JM
150 °C
T
stg
-55 ... +150 °C
T
L
1.6 mm (0.062 in.) from case for 10 s 300 °C
Symbol Test Conditions Characteristic Values
(T
J
= 25°C, unless otherwise specified)
min. typ. max.
V
DSS
V
GS
= 0 V, I
D
= 250 mA 500 V
V
GS(th)
V
DS
= V
GS
, I
D
= 4 mA 2 4 V
I
GSS
V
GS
= ±20 V
DC
, V
DS
= 0 ±100 nA
I
DSS
V
DS
= V
DSS
T
J
= 25°C 100 mA
V
GS
= 0 V T
J
= 125°C1mA
R
DS(on)
V
GS
= 10 V, I
D
= 0.5 I
D25
0.15 W
Pulse test, t £ 300 ms, duty cycle d £ 2 %
V
DSS
= 500 V
I
D(cont)
=32A
R
DS(on)
= 0.15 W
t
rr
< 250 ns
IXFJ 32N50Q
HiPerFET
TM
Power MOSFETs
Q-Class
