1. General description
The 74LV125 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC125 and 74HCT125.
The 74LV125 provides four non-inverting buffer/line drivers with 3-state outputs. The
3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE
causes the outputs to assume a high-impedance OFF-state.
2. Features
n Wide operating voltage: 1.0 V to 5.5 V
n Optimized for low voltage applications: 1.0 V to 3.6 V
n Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
n Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25 °C
n Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
=25°C
n ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
n Multiple package options
n Specified from 40 °Cto+85°C and from 40 °C to +125 °C
3. Ordering information
74LV125
Quad buffer/line driver; 3-state
Rev. 03 — 7 April 2009 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV125N 40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74LV125D 40 °C to +125 °C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LV125DB 40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LV125PW 40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LV125_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 7 April 2009 2 of 15
NXP Semiconductors
74LV125
Quad buffer/line driver; 3-state
4. Functional diagram
5. Pinning information
5.1 Pinning
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer)
mna228
1A 1Y
2
1
3
1OE
2A 2Y
5
4
6
2OE
3A 3Y
9
10
8
3OE
4A 4Y
12
13
11
4OE
mna229
1
EN1
1
3
2
4
6
5
10
8
9
13
11
12
mna227
nOE
nA
nY
Fig 4. Pin configuration DIP14, SO14 Fig 5. Pin configuration SSOP14, TSSOP14
74LV125
1OE V
CC
1A 4OE
1Y 4A
2OE 4Y
2A 3OE
2Y 3A
GND 3Y
001aaj961
1
2
3
4
5
6
7 8
10
9
12
11
14
13
74LV125
1OE V
CC
1A 4OE
1Y 4A
2OE 4Y
2A 3OE
2Y 3A
GND 3Y
001aaj921
1
2
3
4
5
6
7
8
10
9
12
11
14
13
74LV125_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 7 April 2009 3 of 15
NXP Semiconductors
74LV125
Quad buffer/line driver; 3-state
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 packages: above 70 °C the value of P
tot
derates linearly with 12 mW/K.
For SO14 packages: above 70 °C the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
Table 2. Pin description
Symbol Pin Description
1
OE, 2OE, 3OE, 4OE, 1, 4, 10, 13 output enable input (active LOW)
1A, 2A, 3A, 4A 2, 5, 9, 12 data input
1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
V
CC
14 supply voltage
Table 3. Function table
[1]
Control Input Output
nOE nA nY
LLL
LHH
HXZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7.0 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+ 0.5 V
[1]
- ±20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+ 0.5 V
[1]
- ±50 mA
I
O
output current V
O
= 0.5 V to (V
CC
+ 0.5 V) - ±35 mA
I
CC
supply current - 70 mA
I
GND
ground current 70 - mA
T
stg
storage temperature 65 +150 °C
P
tot
total power dissipation T
amb
= 40 °C to +125 °C
[2]
DIP14 - 750 mW
SO14, SSOP14, TSSOP14 - 500 mW

74LV125DB,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Buffers & Line Drivers QUAD BUFR/DRVR OE
Lifecycle:
New from this manufacturer.
Delivery:
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