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ADCMP567BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15
ADCMP567 Data Sheet
Rev. A | Page 6 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
03632-002
PIN 1
INDICATOR
V
EE
24
23 NC
22 V
EE
21 V
CC
GND
–INA
+INA
32 GND
20 V
CC
19 V
EE
18 NC
17 V
EE
GND 9
LEB
10
LEB
11
NC
12
V
DD
13
14
QB 15
V
DD
16
V
CC
V
CC
+INB
–INB
GND
1
2
3
4
5
6
7
8
31
LEA
30
LEA
NC
29
27
QA
26
QA
25
V
DD
28
V
DD
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
NOTES
1. THE RECOMMENDED CONNECTION FOR THE
EXPOSED PAD IS GROUND.
ADCMP567
TOP VIEW
(Not to Scale)
QB
Figure 2. ADCMP567 Pin Configuration
Table 3. ADCMP567 Pin Function Descriptions
Pin No. Mnemonic Function
1 GND Analog Ground.
2 −INA
Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven
in conjunction with the noninverting A input.
3 +INA
Noninverting analog input of the differential input stage for Channel A. The noninverting A input must
be driven in conjunction with the inverting A input.
4 V
CC
Positive Supply Terminal.
5 V
CC
Positive Supply Terminal.
6 +INB
Noninverting analog input of the differential input stage for Channel B. The noninverting B input must
be driven in conjunction with the inverting B input.
7 −INB
Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven
in conjunction with the noninverting B input.
8 GND Analog Ground.
9 GND Analog Ground.
10
LEB
One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven
in conjunction with LEB
.
11 LEB
One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEB
must be driven
in conjunction with LEB.
12 NC No Connect. Do not connect to this pin.
13 V
DD
Logic Supply Terminal.
14
QB
One of two complementary outputs for Channel B.
QB
will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 11) for more information.
15 QB
One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 11) for more information.
16 V
DD
Logic Supply Terminal.
17 V
EE
Negative Supply Terminal.
18 NC No Connect. Do not connect to this pin.
19 V
EE
Negative Supply Terminal.
20 V
CC
Positive Supply Terminal.
21 V
CC
Positive Supply Terminal.
22 V
EE
Negative Supply Terminal.
23 NC No Connect. Do not connect to this pin.
Data Sheet ADCMP567
Rev. A | Page 7 of 14
Pin No. Mnemonic Function
24 V
EE
Negative Supply Terminal.
25 V
DD
Logic Supply Terminal.
26 QA
One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 30) for more information.
27
QA
One of two complementary outputs for Channel A.
QA
will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 30) for more information.
28 V
DD
Logic Supply Terminal.
29 NC No Connect. Do not connect to this pin.
30 LEA
One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA
must be driven
in conjunction with LEA.
31
LEA
One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
in conjunction with LEA
.
32 GND Analog Ground.
EPAD Exposed Pad. The recommended connection for the exposed pad is ground.
ADCMP567 Data Sheet
Rev. A | Page 8 of 14
TIMING INFORMATION
50%
50%
V
REF
± V
OS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
LATCH ENABLE
t
H
t
PDL
t
PDH
t
PLOH
t
PLOL
t
R
t
F
V
IN
V
OD
t
S
t
PL
03633-0-003
Figure 3. System Timing Diagram
The timing diagram in Figure 3 shows the ADCMP567 compare and latch features. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol Timing Description
t
PDH
Input to output high
delay
Propagation delay measured from the time the input signal crosses the reference (± the input offset
voltage) to the 50% point of an output low-to-high transition
t
PDL
Input to output low
delay
Propagation delay measured from the time the input signal crosses the reference (± the input offset
voltage) to the 50% point of an output high-to-low transition
t
PLOH
Latch enable to output
high delay
Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to
the 50% point of an output low-to-high transition
t
PLOL
Latch enable to output
low delay
Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to
the 50% point of an output high-to-low transition
t
H
Minimum hold time
Minimum time after the negative transition of the Latch Enable signal that the input signal must
remain unchanged to be acquired and held at the outputs
t
PL
Minimum latch enable
pulse width
Minimum time that the Latch Enable signal must be high to acquire an input signal change
t
S
Minimum setup time
Minimum time before the negative transition of the Latch Enable signal that an input signal change
must be present to be acquired and held at the outputs
t
R
Output rise time
Amount of time required to transition from a low to a high output as measured at the 20% and 80%
points
t
F
Output fall time
Amount of time required to transition from a high to a low output as measured at the 20% and 80%
points
V
OD
Voltage overdrive Difference between the differential input and reference input voltages
P1-P3P4-P6P7-P9P10-P12P13-P15

ADCMP567BCPZ

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Analog Comparators Dual Ultrafast VTG
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