256K x 16 Static RAM
CY7C1041BN
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06496 Rev. *A Revised August 31, 2006
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
•High speed
—t
AA
= 15 ns
• Low active power
— 1540 mW (max.)
• Low CMOS standby power (L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
and OE features
• Available in Pb-free and non Pb-free 44-pin TSOP II and
molded 44-pin (400-Mil) SOJ packages
Functional Description
The CY7C1041BN is a high-performance CMOS static RAM
organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE
) and Output Enable (OE) LOW while forcing the
Write Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041BN is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
14
15
Logic Block Diagram Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
256K x 16
ARRAY
A
0
A
11
A
13
A
12
A
A
A
16
A
17
A
9
A
10
I/O
0
–I/O
7
OE
I/O
8
–I/O
15
CE
WE
BLE
BHE
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
SOJ
12
13
41
44
43
42
16
15
29
30
V
CC
A
5
A
6
A
7
A
8
A
0
A
1
OE
V
SS
A
17
I/O
15
A
2
CE
I/O
2
I/O
0
I/O
1
BHE
A
3
A
4
18
17
20
19
I/O
3
27
28
25
26
22
21
23
24
V
SS
I/O
6
I/O
4
I/O
5
I/O
7
A
16
A
15
BLE
V
CC
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
I/O
8
A
14
A
13
A
12
A
11
A
9
A
10
NC
TSOP II
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