74AUP1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 9 August 2012 27 of 36
NXP Semiconductors
74AUP1T45
Low-power dual supply translating transceiver; 3-state
13.3 Power-up considerations
A proper power-up sequence always should be followed to avoid excessive supply
current, bus contention, oscillations, or other anomalies. Take the following precautions to
guard against such power-up problems:
• Connect ground before any supply voltage is applied.
• Power-up V
CC(A)
.
• V
CC(B)
can be ramped up along with or after V
CC(A)
.
13.4 Enable times
Calculate the enable times for the 74AUP1T45 using the following formulas:
• t
PZH
(DIR to A) = t
PLZ
(DIR to B) + t
PLH
(B to A)
• t
PZL
(DIR to A) = t
PHZ
(DIR to B) + t
PHL
(B to A)
• t
PZH
(DIR to B) = t
PLZ
(DIR to A) + t
PLH
(A to B)
• t
PZL
(DIR to B) = t
PHZ
(DIR to A) + t
PHL
(A to B)
In a bidirectional application, these enable times provide the maximum delay from the
time the DIR bit is switched until an output is expected. For example, if the 74AUP1T45
initially is transmitting from A to B, then the DIR bit is switched, the B port of the device
must be disabled before presenting it with an input. After the B port has been disabled, an
input signal applied to it appears on the corresponding A port after the specified
propagation delay.
