LTC3122
7
3122fa
For more information www.linear.com/LTC3122
pin FuncTions
SW (Pin 1): Switch Pin. Connect an inductor from this
pin to V
IN
. Keep PCB trace lengths as short and wide as
possible to reduce EMI and voltage overshoot. When V
OUT
≥ V
IN
+ 2V, an internal anti-ringing resistor is connected
between SW and V
IN
after the inductor current has dropped
to near zero, to minimize EMI. The anti-ringing resistor is
also activated in shutdown and during the sleep periods
of Burst Mode operation.
PGND (Pins 2, 13): Power Ground. When laying out your
PCB, provide a short, direct path between PGND and the
output capacitor and tie directly to the ground plane. The
exposed pad is ground and must be soldered to the PCB
ground plane for rated thermal performance.
V
IN
(Pin 3): Input Supply Pin. The device is powered from
V
IN
unless V
OUT
exceeds V
IN
and V
IN
is less than 3V. Place
a low ESR ceramic bypass capacitor of at least 4.7µF from
V
IN
to PGND. X5R and X7R dielectrics are preferred for
their superior voltage and temperature characteristics.
PWM/SYNC (Pin 4): Burst Mode Operation Select and
Oscillator Synchronization. Do not leave this pin floating.
PWM/SYNC = High. Disable Burst Mode Operation and
maintain low noise, constant frequency operation.
PWM/SYNC = Low. The converter operates in Burst
Mode operation, independent of load current.
PWM/SYNC = External CLK. The internal oscillator is
synchronized to the external CLK signal. Burst Mode
operation is disabled. A clock pulse width between
100ns and 2µs is required to synchronize the oscillator.
An external resistor must be connected between RT
and GND to program the oscillator slightly below the
desired synchronization frequency.
In non-synchronized applications, repeated clocking of
the PWM/SYNC pin to affect an operating mode change
is supported with these restrictions:
Boost Mode (V
OUT
> V
IN
): I
OUT
<500µA: ƒ
PWM/SYNC
100Hz, I
OUT
≥ 500µA: ƒ
PWM/SYNC
≤ 5kHz
Buck Mode (V
OUT
< V
IN
): I
OUT
<5mA: ƒ
PWM/SYNC
≤ 5Hz,
I
OUT
≥ 5mA: ƒ
PWM/SYNC
≤ 5kHz
V
CC
(Pin 5): V
CC
Regulator Output. Connect a low-ESR
filter capacitor of at least 4.7µF from this pin to GND to
provide a regulated rail approximately equal to the lower of
V
IN
and 4.25V. When V
OUT
is higher than V
IN
, and V
IN
falls
below 3V, V
CC
will regulate to the lower of approximately
V
OUT
and 4.25V. A UVLO event occurs if V
CC
drops below
1.6V. Switching is inhibited, and a soft-start is initiated
when V
CC
returns above 1.7V.
RT (Pin 6): Frequency Adjust Pin. Connect an external
resistor (R
T
) from this pin to SGND to program the oscil-
lator frequency according to the formula:
R
T
= 57.6/ƒ
OSC
where ƒ
OSC
is in MHz and R
T
is in kΩ.
VC (Pin 7): Error Amplifier Output. A frequency compen-
sation network is connected to this pin to compensate
the control loop. See Compensating the Feedback Loop
section for guidelines.
FB (Pin 8): Feedback Input to the Error Amplifier. Connect
the resistor divider tap to this pin. Connect the top of the
divider to V
OUT
and the bottom of the divider to SGND.
The output voltage can be adjusted from 2.2V to 15V ac-
cording to this formula:
V
OUT
= 1.202V • (1 + R1/R2)
SD (Pin 9): Logic Controlled Shutdown Input. Bringing this
pin above 1.6V enables normal, free-running operation,
forcing this pin below 0.25V shuts the LTC3122 down, with
quiescent current below 1μA. Do not leave this pin floating.
SGND (Pin 10): Signal Ground. When laying out a PC
board, provide a short, direct path between SGND and
the (–) side of the output capacitor.
V
OUT
(Pin 11): Output Voltage Sense and the Source of
the Internal Synchronous Rectifier MOSFET. Driver bias
is derived from V
OUT
. Connect the output filter capacitor
from V
OUT
to PGND, as close to the IC as possible. A
minimum value of 10µF ceramic is recommended. V
OUT
is disconnected from V
IN
when SD is low.
CAP (Pin 12): Serves as the Low Reference for the Syn-
chronous Rectifier Gate Drive. Connect a low ESR filter
capacitor (typically 100nF) from this pin to V
OUT
to provide
an elevated ground rail, approximately 5.6V below V
OUT
,
used to drive the synchronous rectifier.
LTC3122
8
3122fa
For more information www.linear.com/LTC3122
block DiagraM
3122 BD
LTC3122
PWM
LOGIC
AND
DRIVERS
SHUTDOWN SD
CURRENT
SENSE
TSD
V
REF_UP
OSC
SD
OVLO
ANTI-RING
PWM
BURST
SYNC
CONTROL
3
1
L1
11
12
7
8
10
2
13
+
+
ADAPTIVE SLOPE COMPENSATION
I
LIM
REF
4
5
9
LDO
V
BEST
V
IN
V
OUT
6
OSCILLATOR OSC
+
BULK CONTROL
SIGNALS
SOFT-START
VC CLAMP
SD
TSD
OVLO
REFERENCE
UVLO
THERMAL SD
V
REF_UP
1.202V
TSD
SGND
PGND
EXPOSED PAD
RT
V
CC
V
IN
C
IN
R
T
SW
PWM/SYNC
SD
V
IN
1.8V TO 5.5V
C
VCC
4.7µF
C
OUT
I
ZERO
COMP
OVLO
PGND
16.2V
1.202V
g
m
ERROR
AMPLIFIER
V
OUT
CAP
FB
R1
R2
VC
C
PL
V
C
R
PL
C1
100nF
C
C
R
C
C
F
V
OUT
2.2V TO 15V
THE VALUES OF RC, CC, AND CF ARE BASED UPON OPERATING CONDITIONS.
PLEASE REFER TO COMPENSATING THE FEEDBACK LOOP SECTION FOR
GUIDELINES TO DETERMINE OPTIMAL VALUES OF THESE COMPONENTS.
V
IN
+
LTC3122
9
3122fa
For more information www.linear.com/LTC3122
operaTion
The LTC3122 is an adjustable frequency, 100kHz to 3MHz
synchronous boost converter housed in either a 12-lead
4mm × 3mm DFN or a thermally enhanced MSOP pack
-
age. The LTC3122 offers the unique ability to start-up
and regulate the output from inputs as low as 1.8V and
continue to operate from inputs as low as 0.5V. Output
voltages can be programmed between 2.2V and 15V. The
device also features fixed frequency, current mode PWM
control for exceptional line and load regulation. The cur
-
rent mode architecture with adaptive slope compensation
provides excellent transient load response and requires
minimal output filtering. An internal 10ms closed loop
soft-start simplifies the design process while minimizing
the number of external components.
With its low R
DS(ON)
and low gate charge internal N-channel
MOSFET switch and P-channel MOSFET synchronous
rectifier, the LTC3122 achieves high efficiency over a wide
range of load current. High efficiency is achieved at light
loads when Burst Mode operation is commanded. Operation
can be best understood by referring to the Block Diagram.
LOW VOLTAGE OPERATION
The LTC3122 is designed to allow start-up from input
voltages as low as 1.8V. When V
OUT
exceeds 2.2V, the
LTC3122 continues to regulate its output, even when V
IN
falls to as low as 0.5V. The limiting factors for the applica-
tion become the availability of the input source to supply
sufficient power to the output at the low voltages, and
the maximum duty cycle. Note that at low input voltages,
small voltage drops due to series resistance become
critical and greatly limit the power deliver
y capability of
the
converter. This feature extends operating times by
maximizing the amount of energy that can be extracted
from the input source.
LOW NOISE FIXED FREQUENCY OPERATION
Soft-Start
The LTC3122 contains internal circuitry to provide closed-
loop soft-start operation. The soft-start utilizes a linearly
increasing ramp of the error amplifier reference voltage
from zero to its nominal value of 1.202V in approximately
10ms, with the internal control loop driving V
OUT
from
zero to its final programmed value. This limits the inrush
current drawn from the input source. As a result, the du-
ration of the soft-start is largely unaffected by the size of
the output capacitor or the output regulation voltage. The
closed loop nature of the soft-start allows the converter
to respond to load transients that might occur during
the soft-start inter
val. The soft-start period is reset by a
shutdown command on
SD, a UVLO event on V
CC
(V
CC
<
1.6V), an overvoltage event on V
OUT
(V
OUT
≥ 16.2V), or
an overtemperature event (thermal shutdown is invoked
when the die temperature exceeds 170°C). Upon removal
of these fault conditions, the LTC3122 will soft-start the
output voltage.
Error Amplifier
The non-inverting input of the transconductance error
amplifier is internally connected to the 1.202V reference
and the inverting input is connected to FB. An external
resistive voltage divider from V
OUT
to ground programs
the output voltage from 2.2V to 15V via FB as shown in
Figure 1.
V
OUT
= 1.202V 1+
R1
R2
Selecting an R2 value of 121kΩ to have approximately
10µA of bias current in the V
OUT
resistor divider yields
the formula:
R1 = 100.67•(V
OUT
– 1.202V)
where R1 is in kΩ.
Power converter control loop compensation is set by a
simple RC network between V
C
and ground.
Figure 1. Programming the Output Voltage
3122 F01
FB
LTC3122
1.202V
R2
R1
V
OUT
+

LTC3122EMSE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 15V, 2.5A Synchronous Step-Up DC/DC Converter with Output Disconnect
Lifecycle:
New from this manufacturer.
Delivery:
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