813N252DI-02 DATA SHEET
REVISION 1 08/14/15 16 JITTER ATTENUATOR & FEMTOCLOCK NG
®
MULTIPLIER
Schematic Example
Figure 5 (on next page) shows an example of 813N252DI-02
application schematic. In this example, the device is operated at V
CC
= V
CCX
= V
CCO
= 3.3V. A 10pF parallel resonant 27MHz crystal is
used. Spare placement pads for the load capacitance C1 and C2 are
recommended for frequency accuracy. Depending on the parasitics
of the printed circuit board layout, these values might require a slight
adjustment to optimize the frequency accuracy. Crystals with other
load capacitance specifications can be used. This will required
adjusting C1 and C2.
An Optional 3-pole filter can also be used for additional spur
reduction. It is recommended that the loop filter components be laid
out for the 3-pole option. This will allow the flexibility for the 2-pole
filter to be used.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The 813N252DI-02 provides separate
power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1µF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
