© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 8
1 Publication Order Number:
MC14027B/D
MC14027B
Dual J-K Flip-Flop
The MC14027B dual J−K flip−flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip−flop. These devices may be
used in control, register, or toggle functions.
Features
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout
• Logic Edge−Clocked Flip−Flop Design
• Logic State is Retained Indefinitely with Clock Level Either High or
Low; Information is Transferred to the Output Only on the
Positive−Going Edge of the Clock Pulse
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Pin−for−Pin Replacement for CD4027B
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage Range −0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
± 10 mA
P
D
Power Dissipation, per Package
(Note 1)
500 mW
T
A
Ambient Temperature Range −55 to +125 °C
T
stg
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature
(8−Second Soldering)
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤ (V
in
or V
out
) ≤ V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
MARKING DIAGRAM
SOIC−16
D SUFFIX
CASE 751B
14027BG
AWLYWW
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
G = Pb−Free Indicator
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
1
16
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
R
B
C
B
Q
B
Q
B
V
DD
S
B
J
B
K
B
R
A
C
A
Q
A
Q
A
V
SS
S
A
J
A
K
A
PIN ASSIGNMENT
