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MAX9218ECM/V+

P1-P3P4-P6P7-P9P10-P12P13-P15
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
4 _______________________________________________________________________________________
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
and V
TL
.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25°C.
Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V
CC
- 0.3V. PWRDWN is ≤ 0.3V.
Note 4: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 5: C
L
includes probe and test jig capacitance.
AC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to 3.6V, C
L
= 8pF, PWRDWN = high, differential input voltage ⏐V
ID
⏐ = 0.1V to 1.2V, input common-mode voltage
V
CM
= ⏐V
ID
/2⏐ to V
CC
- ⏐V
ID
/2⏐, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC_
= +3.3V, ⏐V
ID
⏐ = 0.2V, V
CM
=
1.2V, T
A
= +25°C.) (Notes 4, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFCLK TIMING REQUIREMENTS
Period t
T
28.57 333.00 ns
Frequency f
CLK
3 35 MHz
Frequency Variation Δf
CLK
REFCLK to serializer PCLK_IN -2.0 +2.0 %
Duty Cycle DC 40 50 60 %
Transition Time t
TRAN
20% to 80% 6 ns
SWITCHING CHARACTERISTICS
RNG1, RNG0 = high 3.2 4.4
Output Rise Time
t
R
Figure 3
RNG1, RNG0 both not high
simultaneously
3.8 5.5
ns
RNG1, RNG0 = high 2.7 4.5
Output Fall Time t
F
Figure 3
RNG1, RNG0 both not high
simultaneously
3.6 5.3
ns
PCLK_OUT High Time t
HIGH
Figure 4
0.4 x
t
T
0.45 x
t
T
0.6 x
t
T
ns
PCLK_OUT Low Time t
LOW
Figure 4
0.4 x
t
T
0.45 x
t
T
0.6 x
t
T
ns
Data Valid Before PCLK_OUT t
DVB
Figure 5 0.35 x t
T
0.4 x t
T
ns
Data Valid After PCLK_OUT t
DVA
Figure 5 0.35 x t
T
0.4 x t
T
ns
Input-to-Output Delay t
DELAY
Figure 6
2.575 x
t
T
+
8.5
2.725 x
t
T
+
12.8
ns
PLL Lock to REFCLK t
PLLREF
Figure 7
16385 x
t
T
ns
Power-Down Delay t
PDD
Figure 7 100 ns
Output Enable Time t
OE
Figure 8 30 ns
Output Disable Time t
OZ
Figure 9 30 ns
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
_______________________________________________________________________________________ 5
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY
MAX9218 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
31277 11 15 19 23
10
20
30
40
50
60
70
80
0
335
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
CCO
)
MAX9218 toc02
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
3.02.72.42.1
1
2
3
4
5
6
7
0
1.8 3.3
RNG1 = RNG0 = HIGH
t
R
t
F
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
CCO
)
MAX9218 toc03
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
3.02.72.42.1
1
2
3
4
5
6
7
0
1.8 3.3
RNG1 = RNG0 = BOTH NOT HIGH
t
R
t
F
BIT-ERROR RATE
vs. CABLE LENGTH
MAX9218 toc04
CAT5e CABLE LENGTH (m)
BIT-ERROR RATE
161284
10
-11
10
-12
10
-13
10
-14
10
-10
020
35MHz CLOCK
700Mbps DATA RATE
FOR <12m, BER < 10
-12
CAT5e
Typical Operating Characteristics
(V
CC
_ = +3.3V, C
L
= 8pF, T
A
= +25°C, unless otherwise noted.)
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
6 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1R/F
Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT for
latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a falling latch
edge. Internally pulled down to GND.
2 RNG1
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input
frequency. Internally pulled down to GND.
3V
CCLVDS
LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
4 IN+ Noninverting LVDS Serial Data Input
5 IN- Inverting LVDS Serial Data Input
6 LVDS GND LVDS Supply Ground
7 PLL GND PLL Supply Ground
8V
CCPLL
PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
9 RNG0
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input
frequency. Internal pulldown to GND.
10 GND Digital Supply Ground
11 V
CC
Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to GND with
0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value
capacitor closest to the supply pin.
12 REFCLK
LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within ±2% of the serializer
PCLK_IN frequency. Internally pulled down to GND.
13 PWRDWN LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
14 OUTEN
LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving low places
the single-ended outputs in high impedance. Internally pulled down to GND.
15–23 CNTL_OUT [8:0]
LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the rising or
falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held at the last state
when DE_OUT is high.
24 DE_OUT
LVTTL/LVCMOS Data Enable Output. High indicates RGB_OUT[17:0] are active. Low indicates
CNTL_OUT[8:0] are active.
25, 37 V
CCO
GND Output Supply Ground
26, 38 V
CCO
Output Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the
device as possible, with the smallest value capacitor closest to the supply pin.
27 LOCK LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low.
28 PCLK_OUT LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F.
29–36,
39–48
RGB_OUT [17:0]
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are latched into
the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high, and are held at the
last state when DE_OUT is low.
— EP Exposed Pad for Thin QFN Package Only. Connect to GND.
P1-P3P4-P6P7-P9P10-P12P13-P15

MAX9218ECM/V+

Mfr. #:
Buy MAX9218ECM/V+
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes 27-Bit DC-Balanced Deserializer
Lifecycle:
New from this manufacturer.
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