OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

EPF6024ABC256-1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
34 Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) The minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to
5.75 V for input currents less than 100 mA and periods shorter than 20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum V
CC
rise time is 100 ms. V
CC
must rise monotonically.
(5) Typical values are for T
A
= 25° C and V
CC
= 3.3 V.
(6) These values are specified under Table 16 on page 33.
(7) The I
OH
parameter refers to high-level TTL or CMOS output current.
(8) The I
OL
parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(9) Capacitance is sample-tested only.
Table 17. FLEX 6000 3.3-V Device DC Operating Conditions Notes (5), (6)
Symbol Parameter Conditions Min Typ Max Unit
V
IH
High-level input voltage 1.7 5.75 V
V
IL
Low-level input voltage –0.5 0.8 V
V
OH
3.3-V high-level TTL output
voltage
I
OH
= –8 mA DC, V
CCIO
= 3.00 V (7) 2.4 V
3.3-V high-level CMOS output
voltage
I
OH
= –0.1 mA DC, V
CCIO
= 3.00 V (7) V
CCIO
–0.2 V
2.5-V high-level output voltage I
OH
= –100 µA DC, V
CCIO
= 2.30 V (7) 2.1 V
I
OH
= –1 mA DC, V
CCIO
= 2.30 V (7) 2.0 V
I
OH
= –2 mA DC, V
CCIO
= 2.30 V (7) 1.7 V
V
OL
3.3-V low-level TTL output
voltage
I
OL
= 8 mA DC, V
CCIO
= 3.00 V (8) 0.45 V
3.3-V low-level CMOS output
voltage
I
OL
= 0.1 mA DC, V
CCIO
= 3.00 V (8) 0.2 V
2.5-V low-level output voltage I
OL
= 100 µA DC, V
CCIO
= 2.30 V (8) 0.2 V
I
OL
= 1 mA DC, V
CCIO
= 2.30 V (8) 0.4 V
I
OL
= 2 mA DC, V
CCIO
= 2.30 V (8) 0.7 V
I
I
Input pin leakage current V
I
= 5.3 V to ground (8) –10 10 µA
I
OZ
Tri-stated I/O pin leakage current V
O
= 5.3 V to ground (8) –10 10 µA
I
CC0
V
CC
supply current (standby) V
I
= ground, no load 0.5 5 mA
Table 18. FLEX 6000 3.3-V Device Capacitance Note (9)
Symbol Parameter Conditions Min Max Unit
C
IN
Input capacitance for I/O pin V
IN
= 0 V, f = 1.0 MHz
8pF
C
INCLK
Input capacitance for dedicated input V
IN
= 0 V, f = 1.0 MHz
12 pF
C
OUT
Output capacitance V
OUT
= 0 V, f = 1.0 MHz
8pF
Altera Corporation 35
FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 18 shows the typical output drive characteristics of 5.0-V and 3.3-V
FLEX 6000 devices with 5.0-V, 3.3-V, and 2.5-V V
CCIO
. When
V
CCIO
= 5.0 V on EPF6016 devices, the output driver is compliant with the
PCI Local Bus Specification, Revision 2.2 for 5.0-V operation. When
V
CCIO
= 3.3 V on the EPF6010A and EPF6016A devices, the output driver
is compliant with the PCI Local Bus Specification, Revision 2.2 for 3.3-V
operation.
Figure 18. Output Drive Characteristics
V
O
Output Voltage (V)
12345
75
I
OL
I
OH
V
CCINT
= 3.3 V
V
CCIO
= 3.3 V
Room Temperature
EPF6010A
EPF6016A
50
25
100
EPF6010A
EPF6016A
V
O
Output Voltage (V)
12345
75
I
OL
I
OH
V
CCINT
= 3.3 V
V
CCIO
= 2.5 V
Room Temperature
50
25
100
V
O
Output Voltage (V)
12345
75
I
OL
I
OH
V
CCINT
= 3.3 V
V
CCIO
= 3.3 V
Room Temperature
EPF6024A
50
25
100
V
O
Output Voltage (V)
12345
75
I
OL
I
OH
V
CCINT
= 3.3 V
V
CCIO
= 2.5 V
Room Temperature
EPF6024A
50
25
100
V
O
Output Voltage (V)
12345
150
120
90
I
OL
I
OH
V
CCINT
= 5.0 V
V
CCIO
= 5.0 V
Room Temperature
V
O
Output Voltage (V)
12345
30
60
90
150
120
I
OL
I
OH
3.3
V
CCINT
= 5.0 V
V
CCIO
= 3.3 V
Room Temperature
EPF6016 EPF6016
60
30
Typical I
O
Output
Current (mA)
Typical I
O
Output
Current (mA)
Typical I
O
Output
Current (mA)
Typical I
O
Output
Current (mA)
Typical I
O
Output
Current (mA)
Typical I
O
Output
Current (mA)
36 Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Timing Model
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
■ LE register clock-to-output delay (t
CO +
t
REG_TO_OUT
)
■ Routing delay (t
ROW +
t
LOCAL
)
■ LE LUT delay (t
DATA_TO_REG
)
■ LE register setup time (t
SU
)
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
Timing simulation and delay prediction are available with the Simulator
and Timing Analyzer, or with industry-standard EDA tools. The
Simulator offers both pre-synthesis functional simulation to evaluate logic
design accuracy and post-synthesis timing simulation with 0.1-ns
resolution. The Timing Analyzer provides point-to-point timing delay
information, setup and hold time analysis, and device-wide performance
analysis.
Figure 19 shows the overall timing model, which maps the possible
routing paths to and from the various elements of the FLEX 6000 device.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

EPF6024ABC256-1

Mfr. #:
Buy EPF6024ABC256-1
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array FPGA - Flex 6000 196 LABs 218 IOs
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet