ICS844246DI Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
ICS844246DGI REVISION A NOVEMBER 28, 2012 13 ©2012 Integrated Device Technology, Inc.
Schematic Layout
Figure 4 shows an example of ICS844246DI-08 application
schematic. The schematic example focuses on functional
connections and is not configuration specific. Refer to the pin
description and functional tables in the datasheet to ensure the
logic control inputs are properly set. Input and output
terminations shown are intended as examples only and may
not represent the exact user configuration.
In this example an 18pF parallel resonant 25MHz crystal is used with
load caps C7 = C6 = 22pF. The load caps are recommended for
frequency accuracy, but these may be adjusted for different board
layouts. Crystals with different load capacities may be used, but the
load capacitors will have to be changed accordingly. If different
crystal types are used, please consult IDT for recommendations.
The schematic example shows two different LVDS output
terminations; the standard termination 100
shunt termination for an
LVDS compliant receiver and an AC coupled termination for a
non-LVDS differential receiver. The AC coupled termination requires
that the designer select the values of R4 and R6 in order to center the
LVDS swing within the common mode range of the receiver. In
addition the designer must make sure that the target receiver will
operate reliably with the LVDS swing, which is reduced relative to
other logic families such as HCSL or LVPECL.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS844246DI provides
separate V
DD
, V
DDA
and V
DDO
pins to isolate any high speed
switching noise at the outputs from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
