NLV74HC174ADR2G

© Semiconductor Components Industries, LLC, 2012
July, 2012 Rev. 12
1 Publication Order Number:
MC74HC174A/D
MC74HC174A
Hex D Flip-Flop with
Common Clock and Reset
HighPerformance SiliconGate CMOS
The MC74HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of six D flipflops with common Clock and
Reset inputs. Each flipflop is loaded with a lowtohigh transition of
the Clock input. Reset is asynchronous and activelow.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity: 162 FETs or 40.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
SOIC16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
1
16
PDIP16
N SUFFIX
CASE 648
1
16
1
16
1
16
MC74HC174AN
AWLYYWWG
1
16
HC174AG
AWLYWW
HC
174A
ALYWG
G
1
16
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
MC74HC174A
http://onsemi.com
2
Figure 1. Pin Assignment
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q4
D4
D5
Q5
V
CC
CLOCK
Q3
D3
D1
D0
Q0
RESET
GND
Q2
D2
Q1
Figure 2. Logic Diagram
PIN 16 = V
CC
PIN 8 = GND
3
4
6
11
13
14
2
5
7
10
12
15
D0
D1
D2
D3
D4
D5
Q0
Q1
Q2
Q3
Q4
Q5
CLOCK
9
RESET
1
DATA
INPUTS
NONINVERTING
OUTPUTS
FUNCTION TABLE
Inputs Output
Reset Clock D Q
L X X L
H H H
H L L
H L X No Change
H X No Change
DESIGN/VALUE TABLE
Design Criteria Value Units
Internal Gate Count* 40.5 ea.
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0
mW
Speed Power Product 0.0075 pJ
*Equivalent to a twoinput NAND gate.
ORDERING INFORMATION
Device Package Shipping
MC74HC174ANG PDIP16
(PbFree)
500 Units / Rail
MC74HC174ADG SOIC16
(PbFree)
48 Units / Rail
MC74HC174ADR2G SOIC16
(PbFree)
2500 / Tape & Reel
MC74HC174ADTR2G TSSOP16
(PbFree)
2500 / Tape & Reel
NLV74HC174ADG* SOIC16
(PbFree)
55 Units / Rail
NLV74HC174ADR2G* SOIC16
(PbFree)
2500 / Tape & Reel
NLV74HC174ADTR2G* TSSOP16
(PbFree)
2500 / Tape & Reel
NLV74HC174ANG* PDIP16
(PbFree)
25 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ100 Qualified and PPAP
Capable
MC74HC174A
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) *0.5 to )7.0 V
V
IN
DC Input Voltage (Referenced to GND) *1.5 to V
CC
)1.5 V
V
OUT
DC Output Voltage (Referenced to GND) (Note 1) *0.5 to V
CC
)0.5 V
I
IN
DC Input Current, per Pin $20 mA
I
OUT
DC Output Current, per Pin $25 mA
I
CC
DC Supply Current, V
CC
and GND Pins $50 mA
T
STG
Storage Temperature Range *65 to )150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds PDIP, SOIC, TSSOP 260
_C
T
J
Junction Temperature Under Bias )150
_C
q
JA
Thermal Resistance PDIP
SOIC
TSSOP
78
112
148
_C/W
P
D
Power Dissipation in Still Air at 85_C PDIP
SOIC
TSSOP
750
500
450
mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% 35% UL 94 V0 @ 0.125 in.
V
ESD
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u100
u500
V
I
LATCHUP
Latchup Performance Above V
CC
and Below GND at 85_C (Note 5)
$300 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I
O
absolute maximum rating must be observed.
2. Tested to EIA/JESD22A114A.
3. Tested to EIA/JESD22A115A.
4. Tested to JESD22C101A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
IN
,
V
OUT
DC Input Voltage, Output Voltage (Referenced to GND) (Note 6) 0 V
CC
V
T
A
Operating Temperature, All Package Types *55 )125
_C
t
r
, t
f
CLOCK Input Rise and Fall Time (Figure 4) V
CC
= 2.0 V
V
CC
= 3.3 V
V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
0
1000
700
500
400
ns
6. Unused inputs may not be left open. All inputs must be tied to a high or lowlogic input voltage level.

NLV74HC174ADR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops HEX D-TYPE FLIP-FLOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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