OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

74F138SJ

P1-P3P4-P6P7-P7
© 2000 Fairchild Semiconductor Corporation DS009478 www.fairchildsemi.com
April 1988
Revised September 2000
74F138 1-of-8 Decoder/Demultiplexer
74F138
1-of-8 Decoder/Demultiplexer
General Description
The F138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input enables
allow parallel expansion to a 1-of-24 decoder using just
three F138 devices or a 1-of-32 decoder using four F138
devices and one inverter.
Features
■ Demultiplexing capability
■ Multiple input enable for easy expansion
■ Active LOW mutually exclusive outputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F138SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F138PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2
74F138
Unit Loading/Fan Out
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Functional Description
The F138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A
0,
A
1,
A
2
) and,
when enabled, provides eight mutually exclusive active
LOW outputs (O
0
–O
7
). The F138 features three Enable
inputs, two active LOW (E
1,
E
2
) and one active HIGH (E
3
).
All outputs will be HIGH unless E
1
and E
2
are LOW and E
3
is HIGH. This multiple enable function allows easy parallel
expansion of the device to a 1-of-32 (5 lines to 32 lines)
decoder with just four F138 devices and one inverter (See
Figure 1). The F138 can be used as an 8-output demulti-
plexer by using one of the active LOW Enable inputs as the
data input and the other Enable inputs as strobes. The
Enable inputs which are not used must be permanently tied
to their appropriate active HIGH or active LOW state.
FIGURE 1. Expansion to 1-of-32 Decoding
Pin Names Description
U.L. Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
A
0
–A
2
Address Inputs 1.0/1.0 20 µA/−0.6 mA
E
1
, E
2
Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA
E
3
Enable Input (Active HIGH) 1.0/1.0 20 µA/−0.6 mA
O
0
–O
7
Outputs (Active LOW) 50/33.3 −1 mA/20 mA
Inputs Outputs
E
1
E
2
E
3
A
0
A
1
A
2
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
HXXXXXHH HHHHHH
XHXXXXHHHHHHHH
XXLXXXHH H HHHHH
LLHLLLLHHHHHHH
LLHHLLHL H HHHHH
LLHLHLHH L HHHHH
LLHHHLHH H LHHHH
LLHLLHHH H HLHHH
LLHHLHHH H HHLHH
LLHLHHHH H HHHLH
LLHHHHHH H HHHHL
3 www.fairchildsemi.com
74F138
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
P1-P3P4-P6P7-P7

74F138SJ

Mfr. #:
Buy 74F138SJ
Manufacturer:
ON Semiconductor
Description:
DECODER/DEMUX 1-OF-8 16SOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet