SMARTSWITCH
TM
NKK Switches • email: smartswitch@nkkswitches.com • Phone (480) 991-0942 • Fax (480) 998-1435 • www.nkksmartswitch.com
2
LCD SPECIFICATIONS
Characteristics of Display
Display Operation Mode FSTN positive
Display Condition Transflective with built-in LED backlight
Viewing Angle Adjustable
Driving Method 1/24 duty. 1/5 bias (built-in driving circuit)
Viewing Area 15.0mm x 10.8mm (horizontal x vertical)
Pixel Format 36 x 24 dots (horizonal x vertical)
Pixel Size 0.36mm x 0.36mm (horizontal x vertical)
Backlight LED White
White LED with
Black & White LCD Mode
Absolute Maximum Ratings (Temperature at 25°C)
Items Symbols Ratings
Supply Voltage for Logics V
DD
–0.3V to +7.0V
Supply Voltage for LCD V
LC
–0.3V to +12.0V
Input Voltage V
I
–0.3V to V
DD
+0.3V
Output Voltage V
O
–0.3V to V
DD
+0.3V
Recommended Operating Conditions (Temperature at 25°C)
Items Symbols Minimum Typical Maximum
Supply Voltage for Logics V
DD
4.5V 5.0V 5.5V
Supply Voltage Black/White V
LC
–– 7.3V ––
Input Voltage V
I
0V –– V
DD
Driving Frequency f
FLM
–– 150Hz ––
DC Characteristics of LCD Drive IC (Temperature at 0°C to 40°C and V
DD
= 5.0V ±10%)
Items Symbols Test Conditions Minimum Typical Maximum Unit
High Level Input Voltage V
IH
0.7 V
DD
V
DD
V
Low Level Input Voltage V
IL
0 0.3 V
DD
V
High Level Input Leakage Current I
LIH
V
I
=
V
DD
10 μA
Low Level Input Leakage Current I
LIL
V
I
=
0V
–10 μA
High Level Output Voltage V
OH
I
OH
= –500μA
V
DD
–0.5 V
Low Level Output Voltage V
OL
I
OL
= 500μA
0.5 V
High Level Output Leakage Current I
LOH
V
O
=
V
DD
10 μA
Low Level Output Leakage Current I
LOL
V
O
=
0V –10 μA
Supply Current I
DD
f
SCP
= 1.0MHz 500 μA
LCD Drive Current I
LC
f
LP
= 2.4kHz V
LC
= 7.3V ~ 7.5V
500 2,000 μA
Timing Characteristics of LCD Drive IC
(Temperature at 0°C to 40°C and V
DD
= 5.0V ±10%)
Items Symbols Minimum Maximum
Clock Operation Frequency f
SCP
6.0MHz
Latch Pulse Frequency f
LP
50kHz
Clock High Level Pulse Width t
CWH
70ns
Clock Low Level Pulse Width t
CWL
70ns
Data Setup Time t
DSD
45ns
Data Hold Time t
DHD
50ns
Data Output Delay Time t
PDO
25ns
Latch Setup Time t
DSL
50ns
Latch Hold Time t
DHL
50ns
Latch High Level Width t
LWH
200ns
FLM Setup Time t
DSF
50ns
FLM Hold Time t
DHF
50ns
SCP, LP Rise/Fall Time t
r
/t
f
15ns
Timing Diagram
*1 Last data on first line
*2 Beginning data on second line
*3 Location of LP signal on first line
t
LWH
t
CWL
t
DSF
t
DHF
t
r
t
f
*
3
t
DSL
t
DHL
*
2
*
1
t
PDO
t
DHD
t
DSD
t
CWH
t
r
t
f
SCP
Din
Dout
LP
FLM
