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NCV8512PW50R2G

P1-P3P4-P6P7-P9P10-P10
NCV8512
http://onsemi.com
7
CIRCUIT DESCRIPTION
Figure 11. Reset and Delay Circuit Wave Forms
V
IN
1.8V V
DT
V
OUT
DELAY
RESET
RESET Threshold
Td
0.45V V
LD
Td
Power on
Reset
Input
V Dip
Under−voltage Secondary
Spike
Output
Overload
REGULATOR CONTROL FUNCTIONS
The NCV8512 contains a microprocessor−compatible
control function RESET
(Figure 11).
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up. After V
OUT
increases above the RESET
threshold, the DELAY timer is started. When the DELAY
timer passes 1.8 V, the RESET
signal goes high. A discharge
of the DELAY timer is started when V
OUT
drops and stays
below the RESET
threshold. When the DELAY timer level
drops below 0.45 V, the RESET
signal is brought low.
The RESET
output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET
signal is valid for V
OUT
as low
as 1.0 V.
Adjustable Reset Function
The reset threshold VRL can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from V
OUT
to the pin R
ADJ
as
displayed in Figure 12. The resistor divider keeps the
voltage above the V
RADJ.TH
(typical 1.31 V) and overrides
the internal threshold detector. Adjust the voltage divider
according to the following relationship:
V
THRES
+ V
RADJ.TH
RADJ1 ) RADJ2
RADJ2
(2)
Where;
V
THRES
is the desired output threshold voltage that starts
the time delay for Power on Reset Delay.
V
RADJ.TH
is the default threshold voltage of 1.31 V typ.
R
ADJ1
is the resistor connected from the 5 V output to the
R
ADJ
pin.
R
ADJ2
is the resistor connected from the R
ADJ
pin to
ground.
If the reset adjust option is not needed, the R
ADJ
pin
should be connected to GND causing the reset threshold to
go to its default value (4.65 V typical).
As an example, select resistors to give a threshold voltage
of 4.0 V. This will allow the delay timer to start when the
output crosses the 4.0 V level.
V
THRES
= 4.0 V = 1.31 V x (R
ADJ1
+ R
ADJ2
) / R
ADJ2
Let R
ADJ2
be 100 kW for low current consumption.
R
ADJ1
= 2.05 x 100 k = 205 kW
With 5 V on the output, the voltage on the R
ADJ
pin will
be 1.64 V.
Figure 12. Adjustable RESET
R
ADJ
to mP and
System
Power
R
RST
V
OUT
C
OUT
RESET
C
DELAY
6.4 V
Delay
NCV8512
to mP and
RESET
Port
R
ADJ1
R
ADJ2
DELAY Function
The reset delay circuit provides a delay (programmable by
external capacitor) on the RESET
output lead.
The DELAY lead provides source current (typically 9 mA)
to the external DELAY capacitor at the following times:
1. During Power Up (once the regulation threshold
has been exceeded).
NCV8512
http://onsemi.com
8
2. After a reset event has occurred and the device is
back in regulation. The DELAY capacitor is
discharged when the regulation (RESET
threshold)
has been violated. When the DELAY capacitor
discharges to 0.45 V, the RESET
signal pulls low.
FLAG/Monitor Function
An on−chip comparator is available to provide an early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the FLAG
pin
will allow the microprocessor time to complete its present
task before shutting down. This function is performed by a
comparator referenced to the bandgap voltage. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (MON) (Figure 13). The typical
threshold is 1.20 V on the MON Pin.
Figure 13. FLAG/Monitor Function
V
BAT
V
IN
MON
V
OUT
C
OUT
V
CC
I/O
RESET
mP
FLAG
RESET
GND
Delay
NCV8512
R
ADJ
R
FLG
R
RST
R
M1
R
M2
APPLICATION NOTES
FLAG MONITOR
Figure 14 shows the FLAG Monitor waveforms taken
from the circuit depicted in Figure 13. As the output voltage
falls (V
OUT
), the Monitor threshold is crossed. This causes
the voltage on the FLAG
output to go low sending a warning
signal to the microprocessor that a RESET
signal may occur
in a short period of time. T
WA RN I NG
is the time the
microprocessor has to complete the function it is currently
working on and get ready for the RESET
shutdown signal.
Figure 14. FLAG Monitor Circuit Waveform
V
OUT
MON
RESET
FLAG Monitor
Ref. Voltage
T
WARNING
FLAG
SETTING THE DELAY TIME
The delay time is controlled by the Reset Delay Low
Voltage, Delay Switching Threshold, and the Delay Charge
Current. The delay follows the equation:
t
DELAY
+
ƪ
C
DELAY
(V
DT
* Reset Delay Low Voltage)
ƫ
Delay Charge Current
Example:
Using C
DELAY
= 33 nF.
Use the typical value for Delay Low Voltage = 0.04 V.
Use the typical value for V
DT
= 1.8 V.
Use the typical value for Delay Charge Current = 9.0 mA.
t
DELAY
+
ƪ
33 nF(1.8 * 0.04 V)
ƫ
9.0 mA
+ 6.45 ms
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturer’s data sheet usually provides this information.
The value for the output capacitor C
OUT
shown in Figure 15
should work for most applications, but is not necessarily the
optimized solution.
Figure 15. Test and Application Circuit Showing
Output Compensation
V
IN
V
OUT
C
OUT
**
10 mF
R
RST
RESET
C
IN
*
0.1 mF
NCV8512
*C
IN
required if regulator is located far from the power supply filter.
**C
OUT
required for stability. Capacitor must operate at minimum
temperature expected.
NCV8512
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9
CALCULATING POWER DISSIPATION IN A
SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 16) is:
P
D(max)
+ [V
IN(max)
* V
OUT(min)
]I
OUT(max)
(1)
) V
IN(max)
I
Q
where:
V
IN(max)
is the maximum input voltage,
V
OUT(min)
is the minimum output voltage,
I
OUT(max)
is the maximum output current for the
application, and
I
Q
is the quiescent current the regulator consumes at
I
OUT(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
q
JA
can be calculated:
R
qJA
+
150
C *
T
A
P
D
(2)
The value of R
q
JA
can then be compared with those in the
package section of the data sheet. Those packages with
R
q
JA
’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
SMART
REGULATOR®
I
Q
Control
Features
I
OUT
I
IN
Figure 16. Single Output Regulator with Key
Performance Parameters Labeled
V
IN
V
OUT
}
HEATSINKS
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of R
q
JA
:
R
qJA
+ R
qJC
) R
qCS
) R
qSA
(3)
where:
R
q
JC
= the junction−to−case thermal resistance,
R
q
CS
= the case−to−heatsink thermal resistance, and
R
q
SA
= the heatsink−to−ambient thermal resistance.
R
q
JC
appears in the package section of the data sheet. Like
R
q
JA
, it too is a function of package type. R
q
CS
and R
q
SA
are
functions of the package type, heatsink and the interface
between them. These values appear in heatsink data sheets
of heat sink manufacturers.
Further mounting and cooling information is available in
the application note, AN1040/D, “Mounting Considerations
for Power Semiconductors” located in the
ON Semiconductor web site.
ORDERING INFORMATION
Device Output Voltage Package Shipping
†
NCV8512PW50G
5.0 V
SOW−16 E Pad
(Pb−Free)
47 Units / Rail
NCV8512PW50R2G 1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
P1-P3P4-P6P7-P9P10-P10

NCV8512PW50R2G

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Buy NCV8512PW50R2G
Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators 5V MICROPOWER 150mA LDO
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