MC74VHCT132AM

© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 6
1 Publication Order Number:
MC74VHCT132A/D
MC74VHCT132A
Quad 2-Input NAND Schmitt
Trigger
The MC74VHCT132A is an advanced high speed CMOS Schmitt
NAND trigger fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
Pin configuration and function are the same as the MC74VHC00,
but the inputs have hysteresis and, with its Schmitt trigger function,
the VHCT132A can be used as a line receiver which will receive slow
input signals.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT132A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V
CC
= 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
High Speed: t
PD
= 4.9 ns (Typ) at V
CC
= 5.0 V
Low Power Dissipation: I
CC
= 2 mA (Max) at T
A
= 25°C
TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: V
OLP
= 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 72 FETs or 18 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
MARKING
DIAGRAMS
TSSOP−14
DT SUFFIX
CASE 948G
1
SOIC−14
D SUFFIX
CASE 751A
1
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
WW, W = Work Week
G or G = Pb−Free Package
VHCT132AG
AWLYWW
1
14
VHCT
132A
ALYWG
G
1
14
(Note: Microdot may be in either location)
MC74VHCT132A
http://onsemi.com
2
Figure 1. Logic Diagram
Y1
A1
1
3
B1
2
Y2
A2
4
6
B2
5
Y3
A3
9
8
B3
10
Y4
A4
12
11
B4
13
Figure 2. Pinout: 14−Lead Packages (Top View)
1314 12 11 10 9 8
21 34567
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
FUNCTION TABLE
Inputs Output
ABY
LLH
LHH
HLH
HHL
ORDERING INFORMATION
Device Package Shipping
MC74VHCT132ADR2G SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74VHCT132ADTRG TSSOP−14
(Pb−Free)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC74VHCT132A
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage – 0.5 to + 7.0 V
V
in
DC Input Voltage – 0.5 to + 7.0 V
V
out
DC Output Voltage – 0.5 to V
CC
+ 0.5 V
I
IK
Input Diode Current − 20 mA
I
OK
Output Diode Current ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 50 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
Derating SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 4.5 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature, All Package Types − 40 + 85
_C
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Symbo
l
Parameter Test Conditions
V
CC
V
T
A
= 25°C T
A
85°C T
A
125°C
Unit
Min Typ Max Min Max Min Max
V
T+
Positive Threshold Voltage 3.0
4.5
5.5
1.7
2.0
2.0
1.6
2.0
2.0
1.6
2.0
2.0
V
V
T−
Negative Threshold Voltage 3.0
4.5
6.0
0.35
0.5
0.6
0.35
0.5
0.6
0.35
0.5
0.6
V
V
H
Hysteresis Voltage 3.0
4.5
5.5
0.30
0.40
0.50
1.20
1.40
1.60
0.30
0.40
0.50
1.20
1.40
1.60
0.30
0.40
0.50
1.20
1.40
1.60
V
V
OH
Minimum High−Level Output
Voltage
I
OH
= −50mA
V
IN
= V
IH
or V
IL
I
OH
= − 50mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
I
OH
= − 4mA
I
OH
= − 8mA
4.5
5.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Maximum Low−Level Output
Voltage
V
IN
= V
IH
or V
IL
I
OL
= 50mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
I
OL
= 4mA
I
OL
= 8mA
4.5
5.5
0.36
0.36
0.44
0.44
0.52
0.52
I
IN
Maximum Input Leakage
Current
V
IN
= 5.5V or
GND
0 to
5.5
± 0.1 ± 1.0 ± 1.0
mA
I
CC
Maximum Quiescent Supply
Current
V
IN
= V
CC
or
GND
5.5 2.0 20 40
mA
I
CCT
Quiescent Supply Current Input: V
IN
= 3.4V 5.5 1.35 1.50 1.65 mA
I
OPD
Output Leakage Current V
OUT
= 5.5V 0.0 0.5 5.0 10
mA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.

MC74VHCT132AM

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Logic Gates 5V Quad 2-Input
Lifecycle:
New from this manufacturer.
Delivery:
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