PHD98N03LT_5 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 05 — 1 December 2006 2 of 12
NXP Semiconductors
PHD98N03LT
N-channel TrenchMOS logic level FET
3. Ordering information
4. Limiting values
Table 2. Ordering information
Type number Package
Name Description Version
PHD98N03LT DPAK plastic single-ended surface-mounted package; 3 leads
(one lead cropped)
SOT428
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
drain-source voltage 25 °C ≤ T
j
≤ 175 °C - 25 V
V
DGR
drain-gate voltage (DC) 25 °C ≤ T
j
≤ 175 °C; R
GS
=20kΩ -25V
V
GS
gate-source voltage - ±20 V
I
D
drain current T
mb
=25°C; V
GS
= 5 V; see Figure 2 and 3 -75A
T
mb
= 100 °C; V
GS
= 5 V; see Figure 2 -66A
I
DM
peak drain current T
mb
=25°C; pulsed; t
p
≤ 10 µs; see Figure 3 - 240 A
P
tot
total power dissipation T
mb
=25°C; see Figure 1 - 111 W
T
stg
storage temperature −55 +175 °C
T
j
junction temperature −55 +175 °C
Source-drain diode
I
S
source current T
mb
=25°C - 75 A
I
SM
peak source current T
mb
=25°C; pulsed; t
p
≤ 10 µs - 240 A
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source
avalanche energy
unclamped inductive load; I
D
=43A;
t
p
= 0.27 ms; V
DS
=15V;R
GS
=50Ω;V
GS
=5V;
starting at T
j
=25°C
- 183 mJ
