Block diagram STM6513
10/29 Doc ID 16490 Rev 2
4 Block diagram
Figure 3. Block diagram
AM00374V2
V
CC
SR1
SR0
TSR
TREC
ADJ
RST2
RST1
V
REF
I
REF
t
SRC
t
REC1
t
REC2
SR logic
Three-state
selector
Oscillator
+
STM6513 Block diagram
Doc ID 16490 Rev 2 11/29
STM6513 hookup with RST1 and RST2, bridging the PS_hold reset pulse during the
microprocessor reset initiated by the STM6513 Smart Reset device:
Figure 4. Typical application diagram
Figure 5. Timing waveforms
AM00375a
V
CC
PMU
Seq.
logic
LD00
...
LD07
PWR
SW
POWER
KEY
RST_n
PS_hold
V
REG
STM6513
TSR
TREC
ADJ
RST1 (PP)
RST2 (OD)
SR0
SR1
V
REG
(PU resistor)
MCU
RST
PS_hold
GPIO1 GPIOn
KEYn
KEY1
Forces PS_hold
high during
reset period
C
tREC
100 kΩ
Factory -
programmed
t
REC2
t
REC1
t
REC1
t
SRC
t
REC2
AM00376V2
POR initiated
SR0, SR1
RST2 (OD)
RST1 (PP)
by C
tREC
(210 ms)
(~1 s)
(~1 s)
Smart Reset™ initiated
(210 ms)
Typical operating characteristics STM6513
12/29 Doc ID 16490 Rev 2
5 Typical operating characteristics
Figure 6. Smart Reset delay t
SRC
vs. temperature and supply voltage V
CC
,
TSR = V
SS
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
–60 –40 –20 0 20 40 60 80 100 120 140
Temperature [˚C]
t
SRC
[s]
5.5 V 3.3 V
AM00632

STM6513REIEDG6F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Supervisory Circuits Smart reset Smart reset
Lifecycle:
New from this manufacturer.
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