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STM6513REIEDG6F
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P29
Bloc
k diagram
STM6513
10/29
Doc ID 16490 Re
v 2
4 Bloc
k
diag
ram
Fi
gur
e 3.
Bl
oc
k dia
gra
m
AM00374V2
V
CC
SR1
SR0
TSR
TREC
ADJ
RST2
RST1
V
REF
I
REF
t
SRC
t
REC1
t
REC2
SR logic
Three-state
selector
Oscillator
+
–
STM651
3
Block diagram
Doc ID 16490 Re
v 2
11/29
STM6513 hookup with RST1 and RST2
, bridging the PS_hold reset pulse dur
ing the
microprocessor reset initiated b
y the STM6513
Smar
t Res
et de
vice:
Figur
e 4
.
T
ypi
cal
ap
pli
cat
ion
di
agram
Figure 5
.
Timing
waveforms
AM00375a
V
CC
PMU
Seq.
logic
LD00
...
LD07
PWR
SW
POWER
KEY
RST_n
PS_hold
V
REG
STM6513
TSR
TREC
ADJ
RST1 (PP)
RST2 (OD)
SR0
SR1
V
REG
(PU resistor)
MCU
RST
PS_hold
GPIO1
GPIOn
KEYn
KEY1
Forces PS_hold
high during
reset period
C
tREC
100 k
Ω
Factory -
programmed
t
REC2
t
REC1
t
REC1
t
SRC
t
REC2
AM00376V2
POR initiated
SR0, SR1
RST2 (OD)
RST1 (PP)
by C
tREC
(210 ms)
(~1 s)
(~1 s)
Smart Reset™ initiated
(210 ms)
Typical
oper
ating char
acteristics
STM6513
12/29
Doc ID 16490 Re
v 2
5
T
ypical operating characteristics
Figure 6
.
Smar
t Reset d
elay t
SR
C
vs. t
e
mpera
ture and supply vo
l
tage V
CC
,
TSR = V
SS
2
2.
1
2.
2
2.
3
2.
4
2.
5
2.
6
2.
7
2.
8
2.
9
3
–60
–40
–20
0
20
40
60
80
100
120
140
T
emp
er
at
u
r
e [
˚
C
]
t
SR
C
[s]
5.
5 V
3.
3 V
AM00632
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P29
STM6513REIEDG6F
Mfr. #:
Buy STM6513REIEDG6F
Manufacturer:
STMicroelectronics
Description:
Supervisory Circuits Smart reset Smart reset
Lifecycle:
New from this manufacturer.
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