CY62136EV30LL-45ZSXIT

CY62136EV30 MoBL
®
Document Number: 38-05569 Rev. *I Page 4 of 18
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential
[4, 5]
... –0.3 V to 3.9 V (V
CC MAX
+ 0.3 V)
DC voltage applied to outputs
in High Z state
[4, 5]
.......... –0.3 V to 3.9 V (V
CC MAX
+ 0.3 V)
DC input voltage
[4, 5]
....... –0.3 V to 3.9 V (V
CC MAX
+ 0.3 V)
Output current into outputs (LOW) .............................20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch up current .....................................................> 200 mA
Operating Range
Device Range
Ambient
Temperature
V
CC
[6]
CY62136EV30LL Industrial –40 °C to +85 °C 2.2 V–3.6 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
45 ns
Unit
Min Typ
[7]
Max
V
OH
Output HIGH voltage I
OH
= –0.1 mA V
CC
= 2.20 V 2.0 V
I
OH
= –1.0 mA V
CC
= 2.70 V 2.4 V
V
OL
Output LOW voltage I
OL
= 0.1 mA V
CC
= 2.20 V 0.4 V
I
OL
= 2.1 mA V
CC
= 2.70 V 0.4 V
V
IH
Input HIGH voltage V
CC
= 2.2 V to 2.7 V 1.8 V
CC
+ 0.3 V
V
CC
= 2.7 V to 3.6 V 2.2 V
CC
+ 0.3 V
V
IL
Input LOW voltage V
CC
= 2.2 V to 2.7 V –0.3 0.6 V
V
CC
= 2.7 V to 3.6 V –0.3 0.8 V
I
IX
Input leakage current GND < V
I
< V
CC
–1 +1 A
I
OZ
Output leakage current GND < V
O
< V
CC
, output disabled –1 +1 A
I
CC
V
CC
operating supply current f = f
max
= 1/t
RC
V
CC
= V
CCmax,
I
OUT
= 0 mA
CMOS levels
–1520mA
f = 1 MHz 2 2.5
I
SB1
[8]
Automatic CE power-down
current – CMOS inputs
CE > V
CC
0.2 V,
V
IN
> V
CC
– 0.2 V, V
IN
< 0.2 V
f = f
max
(address and data only),
f = 0 (OE
, and WE), V
CC
= 3.60 V
–17A
I
SB2
[8]
Automatic CE power-down
current – CMOS inputs
CE > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2V, f = 0,
V
CC
= 3.60 V
–17A
Notes
4. V
IL(min.)
= –2.0 V for pulse durations less than 20 ns.
5. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after V
CC
stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25 °C.
8. Chip enable (CE
) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB1
/ I
SB2
/ I
CCDR
specification. Other inputs can be left floating.
CY62136EV30 MoBL
®
Document Number: 38-05569 Rev. *I Page 5 of 18
Capacitance
Parameter
[9]
Description Test Conditions Max Unit
C
IN
Input capacitance T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(typ)
10 pF
C
OUT
Output capacitance 10 pF
Thermal Resistance
Parameter
[9]
Description Test Conditions
48-ball VFBGA
Package
44-pin TSOP II
Package
Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
75 77 C/W
JC
Thermal resistance
(junction to case)
10 13 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
Parameters 2.50 V 3.0 V Unit
R1 16667 1103
R2 15385 1554
R
TH
8000 645
V
TH
1.20 1.75 V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
CY62136EV30 MoBL
®
Document Number: 38-05569 Rev. *I Page 6 of 18
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
[10]
Max Unit
V
DR
V
CC
for data retention 1.0 V
I
CCDR
[11]
Data retention current V
CC
= 1.0 V, CE > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V
–0.83A
t
CDR
[12]
Chip deselect to data
retention time
0––ns
t
R
[13]
Operation recovery time 45 ns
Data Retention Waveform
Figure 4. Data Retention Waveform
[14]
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25 °C.
11. Chip enable (CE
) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB1
/ I
SB2
/ I
CCDR
specification. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100 s or stable at V
CC(min.)
> 100 s.
14. BHE
.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.

CY62136EV30LL-45ZSXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 2Mb 3V 45ns 128K x 16 LP SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union