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FT24C512A-USG-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Fremont Micro Devices FT24C512A
© 2009 Fremont Micro Devices Inc. DS3009E-page1
Two-Wire Serial EEPROM
512K (8-bit wide)
FEATURES
Low voltage and low power operations:
FT24C512A: V
CC
= 1.8V to 5.5V
Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively).
128 bytes page write mode.
Partial page write operation allowed.
Internally organized: 65,536×8 (512K).
Standard 2-wire bi-directional serial interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed write cycle (5ms maximum).
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) compatibility.
Automatic erase before write operation.
Write protect pin for hardware data protection.
High reliability: typically 1,000,000 cycles endurance.
100 years data retention.
Industrial temperature range (-40
o
C to 85
o
C).
Standard 8-pin DIP/SOP/WSOP/MSOP/TSSOP Pb-free packages.
DESCRIPTION
The FT24C512A series are 524,288 bits of serial Electrical Erasable and Programmable Read Only
Memory, commonly known as EEPROM. They are organized as 65,536 words of 8 bits (one byte) each.
The devices are fabricated with proprietary advanced CMOS process for low power and low voltage
applications. These devices are available in standard 8-lead DIP, 8-lead SOP/WSOP/MSOP and 8-lead
TSSOP packages. A standard 2-wire serial interface is used to address all read and write functions. Our
extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications.
PIN CONFIGURATION
Pin Name Pin Function
A2, A1, A0 Device Address Inputs
SDA Serial Data Input / Open Drain Output
SCL Serial Clock Input
WP Write Protect
NC No-Connect
Table 1
FT24C512A
All three packaging types come in Pb-free certified.
VCC
WP
SCL
SDA
A2
A1
A0
GND
FT24C512A
1
2
3
4
8
7
6
5
8L SOP
8L TSSOP
8L DIP
8L WSOP
8L MSOP
Figure 1: Package Type
ABSOLUTE MAXIMUM RATINGS
Industrial operating temperature: -40
o
C to 85
o
C
Storage temperature: -50
o
C to 125
o
C
Input voltage on any pin relative to ground: -0.3V to V
CC
+ 0.3V
Maximum voltage: 8V
ESD Protection on all pins: >2000V
* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device.
Functional operation of the device at conditions beyond those listed in the specification is not guaranteed.
Prolonged exposure to extreme conditions may affect device reliability or functionality.
Figure 2: Block Diagram
DS3009E-page2 © 2009 Fremont Micro Devices Inc.
FT24C512A
PIN DESCRIPTIONS
(A) SERIAL CLOCK (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of
this clock is to clock data out of the EEPROM device.
(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are
hardwired to either V
IH
or V
IL
. If left unconnected, they are internally recognized as V
IL
.
(C) SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can
be wired-OR with other open-drain output devices.
(D) WRITE PROTECT (WP)
The FT24C512A device has a WP pin to protect the whole EEPROM array from programming.
Programming operations are allowed if WP pin is left un-connected or input to V
IL
. Conversely all
programming functions are disabled if WP pin is connected to V
IH
or V
CC
. Read operations is not
affected by the WP pin’s input level.
MEMORY ORGANIZATION
The FT24C512A devices have 512 pages respectively. Since each page has 128 bytes, random word
addressing to FT24C512A will require 16 bits data word addresses.
DEVICE OPERATION
(A) SERIAL CLOCK AND DATA TRANSITIONS
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when
Serial clock SCL is at V
IL
. Any SDA signal transition may interpret as either a START or STOP
condition as described below.
(B) START CONDITION
With SCL ≥V
IH
, a SDA transition from high to low is interpreted as a START condition. All valid
commands must begin with a START condition.
(C) STOP CONDITION
With SCL ≥ V
IH
, a SDA transition from low to high is interpreted as a STOP condition. All valid read
or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after
a read command. A STOP condition after page or byte write command will trigger the chip into the
STANDBY mode after the self-timed internal programming finish (see Figure 3).
© 2009 Fremont Micro Devices Inc. DS3009E-page3
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

FT24C512A-USG-T

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IC EEPROM 512K I2C 1MHZ 8SOP
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