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MC74HC390ADTR2

P1-P3P4-P6P7-P8
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 2
1 Publication Order Number:
MC74HC390A/D
÷ ÷
High–Performance Silicon–Gate CMOS
The MC74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4–bit counters, each
composed of a divide–by–two and a divide–by–five section. The
divide–by–two and divide–by–five counters have separate clock
inputs, and can be cascaded to implement various combinations of ÷ 2
and/or ÷ 5 up to a ÷ 100 counter.
Flip–flops internal to the counters are triggered by high–to–low
transitions of the clock input. A separate, asynchronous reset is
provided for each 4–bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates
LOGIC DIAGRAM
Q
A
Q
B
Q
C
Q
D
1, 15
4, 12
2, 14
3, 13
5, 11
6, 10
7, 9
PIN 16 = V
CC
PIN 8 = GND
CLOCK A
RESET
CLOCK B
÷ 2
COUNTER
÷ 5
COUNTER
FUNCTION TABLE
Clock
A B Reset Action
X X H Reset
÷ 2 and ÷ 5
X L Increment
÷ 2
X L Increment
÷ 5
SO–16
D SUFFIX
CASE 751B
http://onsemi.com
TSSOP–16
DT SUFFIX
CASE 948F
1
16
PDIP–16
N SUFFIX
CASE 648
1
16
1
16
MARKING
DIAGRAMS
1
16
MC74HC390AN
AWLYYWW
1
16
HC390A
AWLYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
HC
390A
ALYW
1
16
Device Package Shipping
ORDERING INFORMATION
MC74HC390AN PDIP–16 2000 / Box
MC74HC390AD SOIC–16
48 / Rail
MC74HC390ADR2 SOIC–16 2500 / Reel
MC74HC390ADT TSSOP–16 96 / Rail
MC74HC390ADTR2 TSSOP–16
2500 / Reel
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
CLOCK B
b
Q
Ab
RESET b
CLOCK A
b
V
CC
Q
Db
Q
Cb
Q
Bb
CLOCK B
a
Q
Aa
RESET a
CLOCK A
a
GND
Q
Da
Q
Ca
Q
Ba
MC74HC390A
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2
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 50 mA
P
D
Power Dissipation in Still Air, Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
T
stg
Storage Temperature – 65 to + 150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
260
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types – 55 + 125
C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
0
1000
600
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol Parameter Test Conditions
V
CC
V
– 55 to
25 C
85 C 125 C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| 20 µA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| 20 µA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
OH
Minimum High–Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
or V
IL
|I
out
| 2.4 mA
|I
out
| 4.0 mA
|I
out
| 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum Low–Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| 2.4 mA
|I
out
| 4.0 mA
|I
out
| 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND (V
in
or V
out
) V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HC390A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
V
CC
V
Test ConditionsParameterSymbol Unit
125 C 85 C
– 55 to
25 C
V
CC
V
Test ConditionsParameterSymbol
I
in
Maximum Input Leakage
Current
V
in
= V
CC
or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 µA
6.0 4 40 160 µA
NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
f
= t
f
= 6 ns)
Guaranteed Limit
Symbol Parameter
V
CC
V
– 55 to
25 C
85 C 125 C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
10
15
30
50
9
14
28
45
8
12
25
40
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock A to QA
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
24
20
80
45
30
26
90
50
36
31
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock A to QC
(QA connected to Clock B)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
200
160
58
49
250
185
65
62
300
210
70
68
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock B to QB
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock B to QC
(Figures 1 and 3)
2.0
3.0
4.5
6.0
90
56
37
31
105
70
46
39
180
100
56
48
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock B to QD
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
ns
t
PHL
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
3.0
4.5
6.0
80
48
30
26
95
65
38
33
110
75
44
39
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
C
in
Maximum Input Capacitance — 10 10 10 pF
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Counter)*
35
pF
* Used to determine the no–load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
P1-P3P4-P6P7-P8

MC74HC390ADTR2

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Manufacturer:
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IC COUNTER RPPL DUAL 4ST 16TSSOP
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